Rainbow Electronics ATmega103L - Manual (Page 73)

ATmega603/103
73
For details in the timing for the SRAM interface, please refer to Figure 78, Table 46, Table 47, Table 48, and Table 49 in
section “DC Characteristics” on page 105.
Figure 50. External SRAM connected to the AVR
Figure 51. External SRAM Access Cycle without wait states
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
D Q
G
Port A
ALE
Port C
RD
WR
AVR
System Clock Ø
ALE
WR
RD
Data / Address [7..0]
Data / Address [7..0]
Address [15..8]
Address
Address
Address
T1 T2 T3
Prev. Address
Prev. Address
Prev. Address
Data
Data
Wr
ite
Read
Address
Address