Rainbow Electronics ATmega103L - Manual (Page 59)

ATmega603/103
59
UART
The ATmega603/103 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and
Transmitter (UART). The main features are:
• Baud rate generator that can generate a large number of baud rates (bps)
• High baud rates at low XTAL frequencies
• 8 or 9 bits data
• Noise filtering
• Overrun detection
• Framing Error detection
• False Start Bit detection
• Three separate interrupts on TX Complete, TX Data Register Empty and RX Complete
Data Transmission
A block schematic of the UART transmitter is shown in Figure 41 .
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDR. Data is transferred
from UDR to the Transmit shift register when:
• A new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift
register is loaded immediately.
• A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift
register is loaded when the stop bit of the character currently being transmitted has been shifted out.
If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDR to the shift register. At this time the UDRE
(UART Data Register Empty) bit in the UART Status Register, USR, is set. When this bit is set (one), the UART is ready to
receive the next character. Writing to UDR clears UDRE. At the same time as the data is transferred from UDR to the
10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9 bit data word is
selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Trans-
mit shift register.