Rainbow Electronics ATmega103L - Manual (Page 27)

ATmega603/103
27
Power-On Reset
A Power-On Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 23, an internal timer
clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after V
CC
has
reached the Power-On Threshold voltage - V
POT
, regardless of the V
CC
rise time (see Figure 24). The Fuse bits SUT1 and
SUT0 is used to select start-up time as indicated in Table 6. A “0” in the table indicates that the fuse is programmed.
The user can select the start-up time according to typical oscillator start-up time. The number of WDT oscillator cycles used
for each time-out except for SUT = 00 is shown in Table 7. The frequency of the watchdog oscillator is voltage dependent
as shown in “Typical characteristics” on page 110.
The setting SUT 1/0 = 00 starts the MCU after 5 CPU clock cycles, and can be used when an external clock signal is
applied to the XTAL1 pin. This setting does not use the WDT oscillator, and enables very fast start-up from the sleep
modes power down or power save if the clock signal is present during sleep. For details, refer to the programming specifi-
cation starting on page 92.
If the built-in start-up delay is sufficient, RESET can be connected to V
CC
directly or via an external pull-up resistor. By hold-
ing the pin low for a period after V
CC
has been applied, the Power-On Reset period can be extended. Refer to Figure 25 for
a timing example on this.
Figure 24. MCU Start-Up, RESET Tied to V
CC
.
Table 7. Number of watchdog oscillator cycles
SUT 1/0 Time-out at V
CC
= 5V Number of WDT cycles
01 0.5 ms 512
10 4.0 ms 4K
11 16.0 ms 16K
VCC
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST