Rainbow Electronics ATmega103L - Manual (Page 102)

ATmega603/103
102
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial interface while RESET is pulled to GND,
or when PEN is low during Power-On Reset. The serial interface consists of pins SCK, RXD/PDI (input) and TXD/PDO
(output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase
instructions can be executed.
For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first exe-
cute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the Program
and EEPROM arrays into $FF.
The Program and EEPROM memory arrays have separate address spaces:
ATmega603: $0000 to $7FFF for Program memory and $0000 to $07FF for EEPROM memory.
ATmega103: $0000 to $FFFF for Program memory and $0000 to $0FFF for EEPROM memory.
Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The
minimum low and high periods for the serial clock (SCK) input are defined as follows:
Low: > 2 XTAL1 clock cycles
High: > 2 XTAL1 clock cycles
Serial Programming Algorithm
When writing serial data to the ATmega603/103, data is sampled by the ATmega 103 on the rising edge of SCK. When
reading data from the ATmega603/103, data is clocked on the falling edge of SCK. See Figure 77. for an explanation. To
program and verify the ATmega103/L in the serial programming mode, the following sequence is recommended (See 4-
byte instruction formats in Table 45.):
1. Power-up sequence: Apply power between V
CC
and GND while RESET and SCK are set to ’0’. The RESET signal
must be kept low during the complete serial programming session. If a crystal is not connected across pins XTAL1
and XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer can not guarantee that SCK is
held low during power-up. In this case, RESET must be given a positive pulse of at least two XTAL1 cycles duration
after SCK has been set to ’0’.
As an alternative to using the RESET signal, PEN can be held low during Power On Reset while SCK is set to ’0’. In
this case, only the PEN value at Power On Reset is important. If a crystal is not connected across pins XTAL1 and
XTAL2, apply a clock signal to the XTAL1 pin. If the programmer cannot guarantee that SCK is held low during power-
up, the PEN method cannot be used.The device must be powered down in order to commence normal operation when
using this method.
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin
PE0(PDI/RXD).
3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the
second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the
echo is correct or not, all 4 bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a
positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is
no functional device connected.
4. If a chip erase is performed (must be done to erase the Flash), wait at least (2 x t
WD_FLASH
), give RESET a positive
pulse of at least two XTAL1 cycles duration after SCK has been set to ’0’, and start over from Step 2.
5. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 7
LSB of the address and data together with the Load Program Memory Page instruction. The Program Memory Page
is stored by loading the Write Program Memory Page instruction with the 9 MSB of the address. The next page can
be written after t
WD_FLASH
, i.e., writing 256 bytes takes t
WD_FLASH
. Accessing the serial programming interface before
the Flash write operation completes can result in incorrect programming.
6. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appro-
priate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If
polling is not used, the user must wait at least t
WD_EEPROM
before issuing the next byte. (Please refer to Table 43)