Rainbow Electronics ATmega103L - Manual (Page 66)

ATmega603/103
66
• Bit 4 - ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog
Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to
the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared
if it has become set before the operation.
•
Bit 3 - ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated.
When cleared (zero), the interrupt is disabled.
•
Bit 2 - ACIC: Analog Comparator Input Capture enable
When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator.
The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize
the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no con-
nection between the analog comparator and the Input Capture function is given. To make the comparator trigger the
Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).
•
Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are
shown in Table 26.
When changing the ACIS1/ACIS0 bits, The Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable
bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed.
Caution: Using the SBI or CBI instruction on other bits than ACI in this register, will write a one back into ACI if it is read as
set, thus clearing the flag.
Analog to Digital Converter
Feature list:
• 10-bit Resolution
• ±2 LSB absolute accuracy
• 0.5 LSB Integral Non-Linearity
• 70 - 280
µ
s conversion time
• Up to 14 kSPS
• 8 Multiplexed Input Channels
• Interrupt on ADC conversion complete.
• Sleep Mode Noise Canceler
The ATmega603/103 features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Mul-
tiplexer which allows each pin of Port F to be used as an input for the ADC. The ADC contains a Sample and Hold Amplifier
which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC
is shown in Figure 45.
The ADC has two separate analog supply voltage pins, AV
CC
and AGND. AGND must be connected to GND, and the volt-
age on AV
CC
must not differ more than
±
0.3 V from V
CC
. See the section “ADC Noise Canceling Techniques” on page 71
on how to connect these pins.
Table 26. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle
0 1 Reserved
1 0 Comparator Interrupt on Falling Output Edge
1 1 Comparator Interrupt on Rising Output Edge