Rainbow Electronics ATmega103L - Manual (Page 43)

ATmega603/103
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lost after a wake-up from power down, due to the unstable clock signal. The user is advised to wait for at least one
second before using Timer/Counter0 after power-up or wake-up from power down.
• Description of wake up from power save mode when the timer is clocked asynchronously: When the interrupt condition is
met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at
least one before the processor can read the counter value. To execute the corresponding Timer/Counter0 interrupt
routine, the global interrupt bit in SREG must have been set. Otherwise, the part will still wake up from power down, but
continues to execute the sleep command. The interrupt flags are updated 3 processor cycles after the processor clock
has started. During these cycles, the processor executes instructions, but the interrupt condition is not readable, and the
interrupt routine has not started yet.
• During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor
cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer
value causing the setting of the interrupt flag. The output compare pin is changed on the timer clock, and is not
synchronized to the processor clock.
16-bit Timer/Counter1
Figure 33 shows the block diagram for Timer/Counter1.
The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped
as described in the specification for the Timer/Counter1 Control Register - TCCR1B. The different status flags (overflow,
compare match and capture event) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found
in the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1
are found in the Timer/Counter Interrupt Mask Register - TIMSK.
When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To
assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one
internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.
The 16-bit Timer/Counter1 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-
ties. Similarly, the high prescaling opportunities makes the Timer/Counter1 useful for lower speed functions or exact timing
functions with infrequent actions.
The Timer/Counter1 supports two Output Compare functions using the Output Compare Register 1 A and B - OCR1A and
OCR1B as the data sources to be compared to the Timer/Counter1 contents. The Output Compare functions include
optional clearing of the counter on compareA match, and actions on the Output Compare pins on both compare matches.