Rainbow Electronics ATmega103L - Manual (Page 34)

ATmega603/103
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Power Down Mode
When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the Power Down Mode. In this mode,
the external oscillator is stopped, while the external interrupts and the Watchdog (if enabled) continue operating. Only an
external reset, a watchdog reset (if enabled), or an external level interrupt can wake up the MCU.
Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for
some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the
watchdog oscillator clock, and if the input has the required level during this time, the MCU will wake up. The period of the
watchdog oscillator is 1 us (nominal) at 5.0V and 25C. The frequency of the watchdog oscillator is voltage dependent as
shown in section “Typical characteristics” on page 110.
When waking up from Power Down Mode, there is a delay from the wake-up condition occurs until the wake-up becomes
effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by
the same SUT fuses that define the reset time-out period. The wake-up period is equal to the clock reset period, as shown
in Table 6.
If the wake-up condition disappears before the MCU wakes up and starts to execute, e.g. a low level on is not held long
enough, the interrupt causing the wake-up will not be executed.
Power Save Mode
When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power Save Mode. This mode is identical
to Power Down, with one exception:
If Timer/Counter0 is clocked asynchronously, i.e. the AS0 bit in ASSR is set, Timer/Counter0 will run during sleep. In addi-
tion to the Power Down wake-up sources, the device can also wake up from either Timer Overflow or Output Compare
event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in TIMSK. To ensure that the
part executes the Interrupt routine when waking up, also set the global interrupt enable bit in SREG.
When waking up from Power Save Mode by an external interrupt, 2 instruction cycles are executed before the interrupt
flags are updated. When waking up by the asynchronous timer, 3 instruction cycles are executed before the flags are
updated. During these cycles, the processor executes instructions, but the interrupt condition is not readable, and the
interrupt routine has not started yet.
Timer/Counters
The ATmega603/103 provides three general purpose Timer/Counters - two 8-bit T/Cs and one 16-bit T/C. Timer/Counter0
can optionally be asynchronously clocked from an external oscillator. This oscillator is optimized for use with a 32.768 kHz
crystal, enabling use of Timer/Counter0 as a Real Time Clock (RTC). Timer/Counter0 has its own prescaler.
Timer/Counters 1 and 2 have individual prescaling selection from the same 10-bit prescaling timer. These Timer/Counters
can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers
the counting.