Rainbow Electronics ATmega103L - Manual (Page 25)

ATmega603/103
25
The most typical program setup for the Reset and Interrupt Vector Addresses are:
Address Labels Code Comments
$0000 jmp RESET ; Reset Handler
$0002 jmp EXT_INT0 ; IRQ0 Handler
$0004 jmp EXT_INT1 ; IRQ1 Handler
$0006 jmp EXT_INT2 ; IRQ2 Handler
$0008 jmp EXT_INT3 ; IRQ3 Handler
$000A jmp EXT_INT4 ; IRQ4 Handler
$000C jmp EXT_INT5 ; IRQ5 Handler
$000E jmp EXT_INT6 ; IRQ6 Handler
$0010 jmp EXT_INT7 ; IRQ7 Handler
$0012 jmp TIM2_COMP ; Timer2 Compare Handler
$0014 jmp TIM2_OVF ; Timer2 Overflow Handler
$0016 jmp TIM1_CAPT ; Timer1 Capture Handler
$0018 jmp TIM1_COMPA ; Timer1 CompareA Handler
$001A jmp TIM1_COMPB ; Timer1 CompareB Handler
$001C jmp TIM1_OVF ; Timer1 Overflow Handler
$001E jmp TIM0_COMP ; Timer0 Compare Handler
$0020 jmp TIM0_OVF ; Timer0 Overflow Handler
$0022 jmp SPI_STC ; SPI Transfer Complete Handler
$0024 jmp UART_RXC ; UART RX Complete Handler
$0026 jmp UART_DRE ; UDR Empty Handler
$0028 jmp UART_TXC ; UART TX Complete Handler
$002A jmp ADC ; ADC Conversion Complete Handler
$002C jmp EE_RDY ; EEPROM Ready Handler
$002E jmp ANA_COMP ; Analog Comparator Handler
;
$0030 MAIN: ldi r16, high(RAMEND); Main program start
$0031 out SPH,r16
$0032 ldi r16, low(RAMEND)
$0033 out SPL,r16
$0034 xxx
... ... ... ...
Reset Sources
The ATmega603/103 has three sources of reset:
• Power-On Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V
POT
).
• External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.
During reset, all I/O registers except the MCU Status register are then set to their initial values, and the program starts exe-
cution from address $0000. The instruction placed in address $0000 must be a JMP - absolute jump instruction to the reset
handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program
code can be placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 6 defines the timing
and electrical parameters of the reset circuitry.