Rainbow Electronics ATmega103L - Manual (Page 107)

ATmega603/103
107
External Data Memory Timing
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 46. External Data Memory Characteristics, 4.0 - 6.0 Volts, No Wait State
Symbol Parameter
6 MHz Oscillator Variable Oscillator
Unit Min Max Min Max
0 1/t
CLCL
Oscillator Frequency 0.0 6.0 MHz
1 t
LHLL
ALE Pulse Width 48.3 0.5t
CLCL
-35.0 (1) ns
2 t
AVLL
Address Valid A to ALE Low 43.3 0.5t
CLCL
-40.0 (1) ns
3a t
LLAX_ST
Address Hold After ALE Low,
ST/STD/STS Instructions
77.3 0.5t
CLCL
-10.0 (2)
ns
3b t
LLAX_LD
Address Hold after ALE Low,
LD/LDD/LDS Instructions
15.0 15.0
ns
4 t
AVLLC
Address Valid C to ALE Low 43.3 0.5t
CLCL
-40.0 (1) ns
5 t
AVRL
Address Valid to RD Low 136.7 1.0t
CLCL
-30.0 ns
6 t
AVWL
Address Valid to WR Low 215.0 1.5t
CLCL
-35.0 (1) ns
7 t
LLWL
ALE Low to WR Low 146.7 186.7 1.0t
CLCL
-20.0 1.0t
CLCL
+20.0 ns
8 t
LLRL
ALE Low to RD Low 146.7 186.7 0.5t
CLCL
-20.0 (2) 0.5t
CLCL
+20.0 (2) ns
9 t
DVRH
Data Setup to RD High 65.0 65.0 ns
10 t
RLDV
Read Low to Data Valid 136.7 1.0t
CLCL
-30.0 ns
11 t
RHDX
Data Hold After RD High 0.0 0.0 ns
12 t
RLRH
RD Pulse Width 146.7 1.0t
CLCL
-20.0 ns
13 t
DVWL
Data Setup to WR Low 53.3 0.5t
CLCL
-30.0 (2) ns
14 t
WHDX
Data Hold After WR High 0.0 0.0 ns
15 t
DVWH
Data Valid to WR High 146.7 1.0t
CLCL
-20.0 ns
16 t
WLWH
WR Pulse Width 63.3 0.5t
CLCL
-20.0 (1) ns
Table 47. External Data Memory Characteristics, 4.0 - 6.0 Volts, 1 Cycle Wait State
Symbol Parameter
6 MHz Oscillator Variable Oscillator
Unit Min Max Min Max
0 1/t
CLCL
Oscillator Frequency 0.0 6.0 MHz
10 t
RLDV
Read Low to Data Valid 303.4 2.0t
CLCL
-30.0 ns
12 t
RLRH
RD Pulse Width 313.4 2.0t
CLCL
-20.0 ns
15 t
DVWH
Data Valid to WR High 313.4 2.0t
CLCL
-20.0 ns
16 t
WLWH
WR Pulse Width 230.0 1.5t
CLCL
-20.0 (2) ns