Rainbow Electronics ATmega103L - Manual (Page 109)

ATmega603/103
109
Figure 78. External RAM Timing
External Clock Drive Waveforms
Figure 79. External Clock Drive Waveforms
Table 50. External Clock Drive
Note: See “External Data Memory Timing” on page 107 for a description of how the duty cycle influences the timing for the External
Data Memory
Symbol Parameter V
CC
= 2.7V to 3.6V V
CC
= 4.0V to 5.5V Units
1/t
CLCL
Oscillator Frequency 0 4 0 6 MHz
t
CLCL
Clock Period 250 167 ns
t
CHCX
High Time 100 67 ns
t
CLCX
Low Time 100 67 ns
t
CLCH
Rise Time 1.6 0.5
µ
s
t
CHCL
Fall Time 1.6 0.5
µ
s
System Clock O
ALE
WR
RD
Data / Address [7..0]
Data / Address [7..0]
Address [15..8]
Address
Address
Address
T1 T2 T3 T4
Prev. Address
Prev. Address
Prev. Address
1
0
4
2 13
3a
5
Note: Clock cycle T3 is only present when external SRAM waitstate is enabled
10
12
14
15
11
8
9
16
7
6
3b
Data
Data
Wr
ite
Read
Addr.
Addr.
VIL1
VIH1