Rainbow Electronics ATmega103L - Manual (Page 61)

ATmega603/103
61
Data Reception
Figure 42. UART Receiver
The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle,
one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection sequence is
initiated. Let sample 1 denote the first zero-sample. Following the 1 to 0-transition, the receiver samples the RXD pin at
sample 8, 9, and 10. If two or more of these three samples are found to be logical ones, the start bit is rejected as a noise
spike and the receiver starts looking for the next 1 to 0-transition.
If however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also
sampled at samples 8, 9, and 10. The logical value found in at least two of the three samples is taken as the bit value. All
bits are shifted into the transmitter shift register as they are sampled. Sampling of an incoming character is shown in Figure
43.
Figure 43. Sampling Received Data
DATA BUS
DATA BUS
UART I/O DATA
REGISTER (UDR)
10(11)-BIT RX
SHIFT REGISTER
UART CONTROL
REGISTER (UCR)
DATA RECOVERY
LOGIC
UART STATUS
REGISTER (USR)
BAUD RATE
GENERATOR
XTAL
RXB8 TXB8 TXEN CHR9 RXEN TXC
TXCIE RXCIE UDRIE
UDRE RXC
RXC
FE DOR
RXC
IRQ
/16
BAUD X 16 BAUD
STORE UDR
PIN CONTROL
LOGIC
RXD
START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT
RXD
RECEIVER
SAMPLING