Rainbow Electronics DS21458 - Manual (Page 4)

DS21455/DS21458 Quad T1/E1/J1 Transceivers
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13. I/O PIN CONFIGURATION OPTIONS..........................................................................................................78
14. LOOPBACK CONFIGURATIONS................................................................................................................80
14.1 P ER -C HANNEL P AYLOAD L OOPBACK .................................................................................. 83
15. ERROR COUNT REGISTERS......................................................................................................................85
15.1 L INE C ODE V IOLATION C OUNT R EGISTER (LCVCR)............................................................ 86
15.1.1 T1 Operation....................................................................................................................86
15.1.2 E1 Operation....................................................................................................................86
15.2 P ATH C ODE V IOLATION C OUNT R EGISTER (PCVCR) .......................................................... 88
15.2.1 T1 Operation....................................................................................................................88
15.2.2 E1 Operation....................................................................................................................88
15.3 F RAMES O UT O F S YNC C OUNT R EGISTER (FOSCR) .......................................................... 89
15.3.1 T1 Operation....................................................................................................................89
15.3.2 E1 Operation....................................................................................................................89
15.4 E-B IT C OUNTER R EGISTER (EBCR)................................................................................... 90
16. DS0 MONITORING FUNCTION ...................................................................................................................91
16.1 T RANSMIT DS0 M ONITOR R EGISTERS ................................................................................ 91
16.2 R ECEIVE DS0 M ONITOR R EGISTERS .................................................................................. 92
17. SIGNALING OPERATION ............................................................................................................................93
17.1 R ECEIVE S IGNALING .......................................................................................................... 93
17.1.1 Processor-Based Receive Signaling............................................................................94
17.1.2 Hardware-Based Receive Signaling ............................................................................94
17.2 T RANSMIT S IGNALING ...................................................................................................... 100
17.2.1 Processor-Based Transmit Signaling ........................................................................100
17.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode.............................104
17.2.3 Software Signaling Insertion Enable Registers, T1 Mode ......................................106
18. PER-CHANNEL IDLE CODE GENERATION ............................................................................................108
18.1 I DLE C ODE P ROGRAMMING E XAMPLES ............................................................................. 109
19. CHANNEL BLOCKING REGISTERS.........................................................................................................113
20. ELASTIC STORES OPERATION...............................................................................................................116
20.1 R ECEIVE S IDE ................................................................................................................. 119
20.1.1 T1 Mode .........................................................................................................................119
20.1.2 E1 Mode .........................................................................................................................119
20.2 T RANSMIT S IDE ............................................................................................................... 120
20.2.1 T1 Mode .........................................................................................................................120
20.2.2 E1 Mode .........................................................................................................................120
20.3 E LASTIC S TORES I NITIALIZATION ...................................................................................... 120
20.4 M INIMUM -D ELAY M ODE ................................................................................................... 121
21. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)................................................................122
22. T1 BIT ORIENTED CODE (BOC) CONTROLLER.....................................................................................123
22.1 T RANSMIT BOC............................................................................................................... 123
22.2 R ECEIVE BOC................................................................................................................. 123
23. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY)........................................127
23.1 H ARDWARE S CHEME (M ETHOD 1) .................................................................................... 127
23.2 I NTERNAL R EGISTER S CHEME B ASED O N D OUBLE -F RAME (M ETHOD 2) ............................. 127
23.3 I NTERNAL R EGISTER S CHEME B ASED O N CRC-4 M ULTIFRAME (M ETHOD 3)...................... 130
24. HDLC CONTROLLERS ..............................................................................................................................141
24.1 B ASIC O PERATION D ETAILS ............................................................................................. 141
24.2 HDLC C ONFIGURATION ................................................................................................... 143
24.2.1 FIFO Control ..................................................................................................................145
24.3 HDLC M APPING .............................................................................................................. 146
24.3.1 Receive...........................................................................................................................146
24.3.2 Transmit .........................................................................................................................148
24.3.3 FIFO Information...........................................................................................................153
24.3.4 Receive Packet Bytes Available .................................................................................153
24.3.5 HDLC FIFOS .................................................................................................................154
24.4 R ECEIVE HDLC C ODE E XAMPLE ...................................................................................... 155
24.5 L EGACY FDL S UPPORT (T1 M ODE ) ................................................................................. 155