Rainbow Electronics DS21458 - Manual (Page 120)

DS21455/DS21458 Quad T1/E1/J1 Transceivers
120 of 270
20.2 Transmit Side
See the IOCR1 and IOCR2 registers for information on clock and I/O configurations.
The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elastic
store is enabled a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. For higher-rate
system clock applications, see the Interleaved PCM Bus Operation section. Controlled slips in the
transmit elastic store are reported in the SR5.3 bit and the direction of the slip is reported in the SR5.4
and SR5.5 bits.
20.2.1 T1 Mode
If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSER will be
ignored every fourth channel. Hence, channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16,
20, 24, and 28) will be ignored. The user can supply frame or multiframe sync pulse to the TSSYNC
input. Also, in 2.048MHz applications, the TCHBLK output will be forced high during the channels
ignored by the framer.
20.2.2 E1 Mode
A 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. The user must supply a frame-
sync pulse or a multiframe-sync pulse to the TSSYNC input.
20.3 Elastic Stores Initialization
There are two elastic-store initializations that can be used to improve performance in certain applications:
elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read
and write pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are
locked to RCLK/TCLK, respectively). See
Table 20-1 for details.
Table 20-1. ELASTIC STORE DELAY AFTER INITIALIZATION
INITIALIZATION REGISTER BIT DELAY
Receive Elastic Store Reset ESCR.2 8 Clocks < Delay < 1 Frame
Transmit Elastic Store Reset ESCR.6 1 Frame < Delay < 2 Frames
Receive Elastic Store Align ESCR.3 ½ Frame < Delay < 1 ½ Frames
Transmit Elastic Store Align ESCR.7 ½ Frame < Delay < 1 ½ Frames