Rainbow Electronics DS21458 - Manual (Page 15)

DS21455/DS21458 Quad T1/E1/J1 Transceivers
15 of 270
3. BLOCK DIAGRAM
Figure 3-1 shows a simplified block diagram highlighting the major components of the DS21458 and
DS21455.
Figure 3-1. DS21458 Block Diagram
RECEIVE
FRAMER
RECEIVE
BACKPLANE
INTERFACE
TRANSMIT
BACKPLANE
INTERFACE TRANSMIT
BACKPLANE
INTERFACE
ELASTIC STORES
SIGNALING BUFFERS
INTERLEAVE BUS
RATE CONVERSION
PAYLOAD LOOPBACK
2 HDLCs
2 HDLCs
TRANSMIT
FRAMER
ELASTIC STORES
SIGNALING BUFFERS
INTERLEAVE BUS
RATE CONVERSION
PAYLOAD LOOPBACK
SYNCHRONIZATION
ALARM MONITORING
SIGNALING EXTRACTION
HDLC EXTRACTION
DS0 CONDITIONING
HDB3/B8ZS DECODER
FRAMING
CRC RECALCULATE(E1)
ALARM INSERTION
SIGNALING INSERTION
HDLC INSERTION
DS0 CONDITIONING
HDB3/B8ZS CODER
JITTER
ATTEN.
RECEIVE
LIU
TRANSMIT
LIU
CLOCK & DATA
RECOVERY
WAVESHAPE
GENERATION
MASTER
CLOCK
CPU INTERFACE
MUX/NON-MUX, INTEL/MOTOROLA
JTAG
TX
OR RX
PATH
BERT
BERT
DS21458
(1 OF 4 TRANSCEIVERS)
BACKPLANE
CLOCK
RCLK
RSER
RSIG
RSIGF
RSYNC
RFSYNC
RMSYNC
RCHCLK
RCHBLK
BPCLK
RSYSCLK
TSYSCLK
TCLK
TSER
TSIG
TSYNC
TSSYNC
TCHCLK
TCHBLK
RTIP
RRING
TTIP
TRING
TPOSI
TNEGO
TCLKO
RNEGO
RCLKO RPOSO 8XCLK
TLCLK
TLINK
RLCLK
RLINK
ESIB
RLOS/LOTC
MCLK1
MCLK2
TRANSCEIVER #2
TRANSCEIVER #3
TRANSCEIVER #4
ESIBS0
ESIBS1
ESIBRD JTDO
JTDI
JTCLK
JTRST
JTMS
REMOTE
LOOP
BACK
LOCAL
LOOP
BACK
FRAMER
LOOP
BACK
JITTER
ATTEN.
TPD