Rainbow Electronics DS21458 - Manual (Page 216)

DS21455/DS21458 Quad T1/E1/J1 Transceivers
216 of 270
35. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT
The DS21455/DS21458 IEEE 1149.1 design supports the standard instruction codes
SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGH-Z,
CLAMP, and IDCODE. The DS21455/DS21458 contain the following as required by IEEE 1149.1
Standard Test-Access Port and Boundary-Scan Architecture:
§ Test Access Port (TAP)
§ TAP Controller
§ Instruction Register
§ Bypass Register
§ Boundary Scan Register
§ Device Identification Register
The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 35-1. JTAG Functional Block Diagram
JTDI JTMS JTCLK JTRST JTDO
TEST ACCESS PORT
CONTROLLER
V
DD
V
DD
V
DD
BOUNDRY SCAN
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
IDENTIFICATION
REGISTER
MUX
SELECT
OUTPUT ENABLE
10k W 10k W 10k W