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Receive side pins, Eceive, 2 receive side pins – Rainbow Electronics DS21458 User Manual

Page 22

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DS21455/DS21458 Quad T1/E1/J1 Transceivers

22 of 270


Signal Name:

TNEGI (DS21455 Only)

Signal Description:

Transmit Negative-Data Input

Signal Type:

Input

Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO
by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function. TPOSI
and TNEGI can be tied together in NRZ applications.

Signal Name:

TCLKI (DS21455 Only)

Signal Description:

Transmit Clock Input

Signal Type:

Input

Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC/TPD pin high. See the LIUC/TPD pin
description for a full explanation of the LIUC/TPD function.


5.2 Receive Side Pins


Signal Name:

RLINK

Signal Description:

Receive Link Data

Signal Type:

Output

T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame.
E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.

Signal Name:

RLCLK

Signal Description:

Receive Link Clock

Signal Type:

Output

T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output.
E1 Mode: A 4kHz to 20kHz clock.

Signal Name:

RCLK

Signal Description:

Receive Clock

Signal Type:

Output

1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.

Signal Name:

RCHCLK

Signal Description:

Receive Channel Clock

Signal Type:

Output

A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel can also be programmed to output a
gated receive-bit clock for fractional T1/E1 applications. Synchronous with RCLK when the receive-side elastic store is
disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for parallel-to-serial conversion
of channel data.

Signal Name:

RCHBLK

Signal Description:

Receive Channel Block

Signal Type:

Output

A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with
RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is
enabled. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and
for per-channel conditioning. See the Channel Blocking Registers section.

Signal Name:

RSER

Signal Description:

Receive Serial Data

Signal Type:

Output

Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive-side elastic store is enabled.