Rainbow Electronics DS21458 - Manual (Page 162)

DS21455/DS21458 Quad T1/E1/J1 Transceivers
162 of 270
25.3.3 Transmit BPV Error Insertion
When IBPV (LIC2.5) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion.
25.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)
The DS21455/DS21458 can transmit the 2.048MHz square-wave synchronization clock. When in E1
mode, to transmit the 2.048MHz clock, set the transmit synchronization clock enable (LIC3.1) = 1.
25.4 MCLK Prescaler
A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at the MCLK pin.
ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs
require an accuracy of ±32ppm for T1 interfaces. A prescaler will divide the 16MHz, 8MHz, or 4MHz clock
down to 2.048MHz. There is an onboard PLL for the jitter attenuator that will convert the 2.048MHz clock to
a 1.544MHz rate for T1 applications. Setting JAMUX (LIC2.3) to a logic 0 bypasses this PLL.
25.5 Jitter Attenuator
The DS21455/DS21458 contain an on-board jitter attenuator that can be set to a depth of either 32 bits or
128 bits via the JABDS bit (LIC1.2). The 128-bit mode is used in applications where large excursions of
wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the
attenuation are shown in
Figure 25-10 and Figure 25-11 . The jitter attenuator can be placed in either the
receive path or the transmit path by appropriately setting or clearing the JAS bit (LIC1.3). Also, the jitter
attenuator can be disabled (in effect, removed) by setting the DJA bit (LIC1.1). Onboard circuitry adjusts
either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to
create a smooth jitter free clock, which is used to clock data out of the jitter attenuator FIFO. It is
acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the
transmit side. If the incoming jitter exceeds either 120UI
P-P
(buffer depth is 128 bits) or 28UI
P-P
(buffer
depth is 32 bits), then the jitter attenuator will divide the internal nominal 32.768MHz (E1) or
24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing.
When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in
Status Register 1 (SR1.4).