Texas Instruments TMS320TCI648x - Manual (Page 80)

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Boot
Program
Host
Controller
Optional
I2C
EEPROM
DSP
ROM
1x RapidIO
2.3.14.2 Bootload Data Movement
2.3.14.3 Device Wakeup
2.3.15 RX Multicast Support, Daisy Chain Operation and Packet Forwarding
2.3.15.1 RX Multicast Support
SRIO Functional Description
4. DSP executes idle instruction.
5. RapidIO ports send Idle control symbols to train PHYs.
6. Host enabled to explore system with RapidIO Maintenance packets.
7. Host identifies, enumerates and initializes the RapidIO device.
8. Host controller configures DSP peripherals through maintenance packets.
•
SRIO Device IDs are set for DSPs (either by pin strapping or by host manipulation)
9. Boot Code sent from host controller to DSP L2 memory base address via NWRITE.
10. DSP CPU is awakened by an interrupt such as a RapidIO DOORBELL packet.
11. Boot Code is executed and normal operation follows.
Figure 41. Bootload Operation
The system host is responsible for writing the bootload data into the DSP’s L2 memory. As such, bootload
is only supported using the direct I/O model, and not the message passing model. Bootload data must be
sent in packets with explicit L2 memory addresses indicating proper destination within the DSP. As part of
the peripheral’s configuration, it should be set up to transfer the desired bootload program to the DSP's
memory through normal DMA bus commands.
Upon completion of the bootload data transfer, the system host issues a DOORBELL interrupt to the DSP.
The RapidIO peripheral processes this interrupt in a manner similar to that described in
Section 4 ,
monitoring the DMA bus write-with-response commands to ensure that the data has been completely
transferred through the DMA. This interrupt wakes up the CPUs by pulling them out of their reset state.
The 16-bit data field of the DOORBELL packet should be configured to interrupt Core 0 by setting a
corresponding ICSR bit as described in
Figure 46 .
Multicast transactions are I/O packets that specify a destination address within the header. This address is
used directly for the internal DSP transfers and is not modified in any way. For this reason, multi-cast
support is limited to groups containing devices with the same memory map, or other devices that can
perform address translation. It is the responsibility of the system designer to pre-determine valid multi-cast
address ranges.
When a packet is received, the packet’s tt field and DestID are checked against the main DeviceID (offset
0x0080) and the MulticastID (see
Table 31 ). If there is no match, the packet is destroyed and not
forwarded to the logical layer. If there is a match, it is forwarded to the logical layer. Since multicast
operations are defined to be operations that do not require responses, they are limited to NWRITE and
SWRITE operations and forwarded to the MAU.
As an endpoint device, the peripheral accepts packets based on the destination ID. Two options exist for
packet acceptance and are mode selectable. The first option is to only accept packets whose DestIDs
match the local deviceID in 0x0080. This provides a level of security. The second option is is system
multicast operation.
Serial RapidIO (SRIO) 80 SPRUE13A – September 2006
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