Texas Instruments TMS320TCI648x - Manual (Page 77)

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2.3.13 Initialization Example
2.3.13.1 Enabling the SRIO Peripheral
2.3.13.2 PLL, Ports, Device ID and Data Rate Initializations
SRIO Functional Description
For multi-segment messages, if the transfer is unsuccessful after 256 times of credit request for the first
segment, the TXU moves to the next queue in the round-robin loop. The TXU tries to send the unsent
message again the next time around the loop. After the first segment is granted outbound credit and is
sent to the physical layer for transmission, all subsequent segments are given 64K attempts to gain
outbound credit. If the TXU is unsuccessful after the 64K attempts, a completion code of 111b is written to
the buffer descriptor, and the message is cancelled with no attempt to resend.
When the device is powered on, the SRIO peripheral is in a disabled state. Before any SRIO specific
initialization can take place, the peripheral needs to be enabled; otherwise, its registers cannot be written,
and the reads will all return a value of zero.
/* Glb enable srio */
SRIO_REGS->GBL_EN = 0x00000001 ;
SRIO_REGS->BLK0_EN = 0x00000001 ; //MMR_EN
SRIO_REGS->BLK5_EN = 0x00000001 ; //PORT0_EN
SRIO_REGS->BLK1_EN = 0x00000001 ; //LSU_EN
SRIO_REGS->BLK2_EN = 0x00000001 ; //MAU_EN
SRIO_REGS->BLK3_EN = 0x00000001 ; //TXU_EN
SRIO_REGS->BLK4_EN = 0x00000001 ; //RXU_EN
SRIO_REGS->BLK6_EN = 0x00000001 ; //PORT1_EN
SRIO_REGS->BLK7_EN = 0x00000001 ; //PORT2_EN
SRIO_REGS->BLK8_EN = 0x00000001 ; //PORT3_EN
To change from 1 lane to 4 lanes there are 2 registers that need to be programmed. See Table 30 .
Table 30. Port Mode Register Settings
Device SP_IP_MODE (offset 0x12004) PER_SET_CNTL (offset 0x0020) Port Mode
Bits 31-30 Bit 8
TMS320TCI6482 0x00 0x00 1x/4p
TMS320TCI6482 0x01 0x01 1x/1x
For example, Enable PLL, 333MHz, 1x/4p (srio4p1x_mode = 1), x20, 125MHz ref. clock, 2.5 Gbps, half
rate:
if (srio4p1x_mode){
rdata = SRIO_REGS->PER_SET_CNTL;
wdata = 0x0000014F; //4p1x
mask = 0x000001FF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata ; // enable PLL
}
else{
wdata = 0x0000004F; // enable PLL, 1p4x
rdata = SRIO_REGS->PER_SET_CNTL;
mask = 0x000001FF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata ; // enable PLL, 1p1x/4x
}
//INIT_MAC0
if (srio4p1x_mode){
SRIO_REGS->SP_IP_MODE = 0x4400003F; // Jadis mltc/rst/pw enable, clear
}
else{
SRIO_REGS->SP_IP_MODE = 0x0400003F; // Jadis mltc/rst/pw enable, clear
}
SPRUE13A – September 2006 Serial RapidIO (SRIO) 77
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