Texas Instruments TMS320TCI648x - Manual (Page 251)

SRIO Registers
PW_DIS field of SP_IP_MODE 231 read support for destination device 189
PW_EN field of SP_IP_MODE 231 read support for source device 188
PW_IRQ field of SP_IP_MODE 231 READ transactions during direct I/O transmission 41
PW_TGT_ID 218 receive CPPI control register 173
PW_TIMER field of SP_IP_DISCOVERY_TIMER 230 receive CPPI interrupt condition clear register 135
receive CPPI interrupt condition routing registers 145
Q
receive CPPI interrupt condition status register 134
QUEUE_ID field of RXU_MAP_Hn 178 receive queue teardown register 172
QUEUEn_FLOW_MASK fields of receiver enabling for SERDES macro
TX_CPPI_FLOW_MASKS[0–7] 169
introduction 30
QUEUEn_IN_ORDER fields of RX_CPPI_CNTL 173
receiver enable bit 126
QUEUEn_RXDMA_CP 167
receive/transmit lockout field for port n 207
QUEUEn_RXDMA_HDP 166
register configuration offset field for LSUn 156
QUEUEn_TEAR_DWN fields of
register introduction 102
RX_QUEUE_TEAR_DOWN 172
reinitialization process field for port n 236
QUEUEn_TEAR_DWN fields of
related documentation 14
TX_QUEUE_TEAR_DOWN 168
reordering of outbound packets 75
QUEUEn_TXDMA_CP 165
reporting thresholds for port n errors
QUEUEn_TXDMA_HDP 164
broken link case 229
queue n receive DMA completion pointer register 167
degraded link case 229
queue n receive DMA head descriptor pointer register
request packets
166
Ftypes and Ttypes 25
queue n transmit DMA completion pointer register 165
in SRIO operation sequence 22
queue n transmit DMA head descriptor pointer register
requirements for external devices 20 164
reset and power down 70 Queue Pointer fields of TX_QUEUE_CNTLn 174
CPPI module 59 queue teardown bits for message reception 172
enable and enable status registers 71 queue teardown bits for message transmission 168
Load/Store module 43 queue transmission order 54
software shutdown details 74
R
reset interrupt enable field for ports 232
RapidIO reset interrupt status field for ports 232
architectural hierarchy 16 reset option CSR for port n 235
RESPONSE_VALID field of SPn_LM_RESP 201 external device requirements 20
response packets features 16
Ftypes and Ttypes 25 features supported in SRIO peripheral 19
in SRIO operation sequence 22 interconnect architecture 18
responses to CPPI (message) transmissions 58 standards 20
response time-out error at LSU or TXU RapidIO DEVICEID1 register 121
reporting enable field 213 RapidIO DEVICEID2 register 122
status field 211 RATE fields
response timer effect on data rate 30
in direct I/O reception 42 RATE field of SERDES_CFGRXn_CNTL 125
in Load/Store module data flow diagram 39 RATE field of SERDES_CFGTXn_CNTL 128
in message reception 47 rate select field for SERDES receiver 126
in message transmission 59 rate select field for SERDES transmitter 128
RETRANSMIT_SUPPRESS field of PE_FEAT 186 RCVD_PKT_NOT_ACCPT field of SPn_ERR_DET 219
retry_count field of TX buffer descriptor 52 RCVD_PKT_OVER_276B field of SPn_ERR_DET 219
RETRY response in message passing 43 RCVD_PKT_WITH_BAD_CRC field of SPn_ERR_DET
219 REV field of PID 111
RCVED_PKT_NOT_ACCPT_EN field of SPn_RATE_EN RIOCLK and RIOCLK signals 25
221
RIORXn and RIORXn signals 25
RCVED_PKT_OVER_276B_EN field of SPn_RATE_EN
RIOTXn and RIOTXn signals 25
221
round-robin access to TX buffer descriptor queues 54
RCVED_PKT_WITH_BAD_CRC_EN field of
routing interrupt conditions to interrupt destinations 93
SPn_RATE_EN 221
routing registers
READ field of DEST_OP 189
for CPPI interrupt conditions 145, 146
READ field of SRC_OP 188
SPRUE13A – September 2006 Index 251
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