Texas Instruments TMS320TCI648x - Manual (Page 118)

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SRIO Registers
Table 45. Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions (continued)
Bit Field Value Description
1 BLK0_EN_STAT Block 0 enable status. Logical block 0 is the set of memory-mapped registers
(MMRs) for the SRIO peripheral.
0 Logical block 0 is in reset with its clock off.
1 Logical block 0 is enabled with its clock running.
0 GBL_EN_STAT Global enable status
0 The peripheral is in reset with all its clocks off.
1 The peripheral is enabled with all its clocks running.
Serial RapidIO (SRIO) 118 SPRUE13A – September 2006
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