Texas Instruments TMS320TCI648x - Manual (Page 140)

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SRIO Registers
Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued)
Bit Field Value Description
1 ICS1 0 LSU1 interrupt condition not detected.
1 LSU1 interrupt condition detected. Non-posted transaction received ERROR response, or error in
response payload.
0 ICS0 0 LSU1 interrupt condition not detected.
1 LSU1 interrupt condition detected. Transaction complete, No errors (posted/non-posted). Enable for
this interrupt is ultimately controlled by the Interrupt Req bit of LSU1_REG4. This allows
enabling/disabling on a per request basis. For optimum LSU performance, interrupt pacing should
not be used on the LSU interrupts.
Serial RapidIO (SRIO) 140 SPRUE13A – September 2006
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