Texas Instruments TMS320TCI648x - Manual (Page 252)

SRIO Registers
SERDES macros for doorbell interrupt conditions 144
for error, reset, and special event (port) interrupt configuration example 35
conditions 149 description 28
for LSU interrupt conditions 147
enable bits 115
RST_CS field of SP_IP_MODE 231
in SRIO component block diagram 26
RST_EN field of SP_IP_MODE 231
in SRIO peripheral block diagram 21
rules for CPPI data traffic 43
PLL enabling 28
RX_CP field of QUEUEn_RXDMA_CP 167
receiver enabling 30
RX_CPPI_CNTL 173
transmitter enabling 33
RX_CPPI_ICCR 135
SERDES receive channel configuration registers 125
RX_CPPI_ICRR 145
SERDES transmit channel configuration registers 128
RX_CPPI_ICRR2 145
serialization/deserialization (SERDES) 21
RX_CPPI_ICSR 134
serial port IP prescaler register 233
RX_CPPI_SECURITY_ENABLE field of ERR_EN 212
Serial RapidIO peripheral. See SRIO peripheral 19
RX_CPPI_SECURITY field of ERR_DET 210
shared buffers
RX_HDP field of QUEUEn_RXDMA_HDP 166
in direct I/O RX operation 42
RX_IO_DMA_ACCESS field of ERR_DET 210
in direct I/O TX READ transaction 41
RX_IO_SECURITY_ENABLE field of ERR_EN 212
in direct I/O TX WRITE transaction 40
RX_QUEUE_TEAR_DOWN 172
in Load/Store module data flow diagram 39
RX buffer descriptor fields 47
in message passing 43
RX buffer descriptor link-list figure 61
in SRIO component block diagram 26
RX buffer descriptor queue teardown 50
SILENCE_TIMER field of SPn_SILENCE_TIMER 238
RX CPPI security error
silent state period for port n 238
reporting enable field 213
single-/multi-segment selection field for message
status bit 211
reception 180
RX I/O DMA access error
single port with 1x or 4x operation 76
reporting enable field 213
small common transport system base device ID 193
status field 211
SOFT_REC field of SPn_CTL_INDEP 236
RX shared buffer
SOFT field of PCR 112
in direct I/O RX operation 42
soft stop bit 112
in direct I/O TX READ transaction 41 soft stop emulation mode 75
in SRIO component block diagram 26
software memory sleep override bit 113
RXU
software requirements for message passing 60
enable bit 119
software shutdown details 74
enable status bits 117, 120 sop field of RX buffer descriptor 47
handling of unavailable outbound credit 76 sop field of TX buffer descriptor 52
in SRIO component block diagram 26
source address field for LSUn 157
RXU_MAP registers
source ID associated with logical/transport error 216
description 177
source ID check or ignore field for message reception
180 introduction 45
SOURCEID field of ID_CAPT 216
S
SOURCEID field of RXU_MAP_Ln 178
security error reporting enable bit for MAU 213 source operations CAR 188
security error reporting enable bit for RXU 213 SP_GEN_CTL 199
security error status bit for MAU 211 SP_IP_DISCOVERY_TIMER 230
security error status bit for RXU 211 SP_IP_IPW_IN_CAPTn 234
SEGMENT_MAPPING field of RXU_MAP_Hn 178 SP_IP_MODE 231
segmentation of outbound direct I/O requests 42 SP_LT_CTL 197
SELF_RST field of SP_IP_MODE 231 SP_MB_HEAD 196
self reset interrupt enable field for ports 231 SP_MODE field of SP_IP_MODE 231
SEND_DBG_PKT field of SPn_CTL_INDEP 236 SP_RT_CTL 198
send debug packet field for port n 237 SPn_ACKID_STAT 202
SERDES_CFGn_CNTL 130 SPn_CS_TX 240
SERDES_CFGRXn_CNTL 125 SPn_CTL 206
SERDES_CFGTXn_CNTL 128 SPn_CTL_INDEP 236
SERDES macro configuration register 130 SPn_ERR_ATTR_CAPT_DBG0 223
252 Index SPRUE13A – September 2006
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