Texas Instruments TMS320TCI648x - Manual (Page 247)

SRIO Registers
limiting which devices can access a mailbox 45 LSU_ICSR 138
line rate versus PLL output clock frequency 29 LSU congestion control flow mask register 162
LINK_STATUS field of SPn_LM_RESP 201 LSU control register 0 155
LINK_TIMEOUT_EN field of SPn_RATE_EN 221 LSU control register 1 156
LINK_TIMEOUT field of SPn_ERR_DET 219 LSU control register 2 157
link maintenance command field for port n 240 LSU control register 3 158
link-request control symbol generation register 200 LSU control register 4 159
link responses LSU control register 5 160
acknowledge or link-response control symbol overdue LSU control register 6 161
at port n LSU interrupt condition clear register 141
rate counting enable field 222 LSU interrupt condition routing registers 147
status field 220 LSU interrupt condition status register 138
link-response valid field 201 LSUn_FLOW_MASKS 162
link status received 201 LSUn_REG0 155
non-outstanding ackID at port n LSUn_REG1 156
rate counting enable field 222 LSUn_REG2 157
status field 220 LSUn_REG3 158
link timeout at port n LSUn_REG4 159
rate counting enable field 222 LSUn_REG5 160
status field 220 LSUn_REG6 161
Little Endian versus Big Endian 68 LSUs
Load/Store module
data path description 39
data flow diagram 39
enable bit 119
data path description 39
enable status bits 117, 120
enable bit 119
handling of unavailable outbound credit 76
enable status bits 117, 120
in Load/Store module data flow diagram 39
power down state 43
in SRIO component block diagram 26
Load/Store units. See LSUs 40
register introduction 35
local configuration space base address CSRs 191, 192
register-load timing diagram 37
lockout field for port n 207
register programming example 38
logical blocks of the SRIO peripheral 71
RX operation 42
logical layer
TX operation 40
content in SRIO data stream 22
definition 16 M
logical layer buffers
MAILBOX_MASK field of RXU_MAP_Ln 178
in packet transmission discussion 75
mailboxes and letters 43
in SRIO component block diagram 26
mailbox field of RX buffer descriptor 47
logical/transport error handling and logging 83
MAILBOX field of RXU_MAP_Ln 178
logical/transport layer address capture CSR 215
mailbox field of TX buffer descriptor 52
logical/transport layer control capture CSR 217
mailbox number associated with logical/transport error
logical/transport layer device ID capture CSR 216 217
logical/transport layer error detect CSR 210 mailbox number masking 45
logical/transport layer error enable CSR 212
mailbox to queue mapping during message reception
logical/transport layer high address capture CSR 214
introduction 44
LOG. See logical layer 23 register descriptions 177
loopback mode 113 maintenance packets
loop bandwidth field for SERDES PLL 130
Ftypes and Ttypes 25
LOS field of SERDES_CFGRXn_CNTL 125 introduction 63
loss of signal detection in SERDES receiver 126 masking mailbox and letter numbers 45
LSBs of address associated with logical/transport error master device mode field 199
215
MAU
LSBs of destination ID associated with logical/transport
enable bit 119
error 216
enable status bits 117, 120
LSBs of source ID associated with logical/transport error
handling of unavailable outbound credit 76
216
in SRIO component block diagram 26
LSU_ICCR 141
MAX_RETRY_EN field of SPn_CTL_INDEP 236
LSU_ICRR0 to LSU_ICRR3 147
SPRUE13A – September 2006 Index 247
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