Texas Instruments TMS320TCI648x - Manual (Page 246)

SRIO Registers
interrupt condition clearing 86 G
interrupt condition clear registers
GBL_EN 116
for CPPI interrupt conditions 135, 137
GBL_EN_STAT 117
for doorbell interrupt conditions 133
global enable bit 116
for error, reset, and special event (port) interrupt
global enable status bit 118
conditions 143
global enabling/disabling of all logical blocks 71
for LSU interrupt conditions 141
interrupt condition routing 93 H
interrupt conditions 85
H_ADDR_CAPT 214
interrupt condition status checking 86
head descriptor pointer field for RX queue n 166
interrupt condition status registers
head descriptor pointer field for TX queue n 164
for CPPI interrupt conditions 134, 136 header fields
for doorbell interrupt conditions 132 doorbell operation 64
for error, reset, and special event (port) interrupt
message request packet 44
conditions 142
hexadecimal notational convention 14
interrupt destinations
HOP_COUNT field of LSUn_REG5 160
controlling interrupt pacing with interrupt rate control
host base device ID lock CSR 194
registers 99
host device mode field 199
narrowing down interrupt sources with help from
interrupt status decode registers
97
I
selecting with interrupt condition routing registers 93
ID_CAPT 216
interrupt error at port n
ID_SIZE field of LSUn_REG4 159
reporting enable field 237
idle error checking disable field for ports 231
status field 237
ILL_TRANS_EN field of SPn_CTL_INDEP 236
interrupt generation 99
ILL_TRANS_ERR field of SPn_CTL_INDEP 236
interrupt handling 100
illegal transaction at LSU, TXU, MAU, or RXU
interrupt pacing (rate control) 99
reporting enable field 212
interrupt rate control registers 154
status field 210
interrupt request field for LSUn 159
illegal transfer error at port n
interrupt status decode registers
reporting enable field 237
description 150
status field 237
introduction 97
INBOUND_ACKID field of SPn_ACKID_STAT 202
mapping example 98
INFO_TYPE field of SPn_ERR_ATTR_CAPT_DBG0
invert polarity bit for SERDES receiver 126
223
invert polarity bit for SERDES transmitter 128
initialization example for message passing 61
INVPAIR field of SERDES_CFGRXn_CNTL 125
initialization example for the SRIO peripheral 77
INVPAIR field of SERDES_CFGTXn_CNTL 128
INITIALIZED_PORT_WIDTH field of SPn_CTL 206
I/O error response at LSU
initialized status bit for ports 205
reporting enable field 212
initialized width field for port n 206
status field 210
in-order reception of message packets 49
IP_PRESCAL 233
in-order requirement bits for RX queues 173
IRQ_EN field of SPn_CTL_INDEP 236
INPUT_ERROR_ENC field of SPn_ERR_STAT 203
IRQ_ERR field of SPn_CTL_INDEP 236
INPUT_ERROR_STP field of SPn_ERR_STAT 203
INPUT_PORT_ENABLE field of SPnCTL 206
L
INPUT_RETRY_STP field of SPn_ERR_STAT 203
L2 memory in Load/Store module data flow diagram 39
input enable field for port n 207
lane select field for port n 206
input error-stopped status bit for ports 204
large common transport system base device ID 193
input retry-stopped status bit for ports 204
large common transport system support field 186
input termination field for SERDES receiver 126
LB field of SERDES_CFGn_CNTL 130
input transmission error status bit for ports 204
LCL_CFG_BAR 192
INTDSTn_DECODE 150
LCL_CFG_HBAR 191
INTDSTn_RATE_CNTL 154
LETTER_MASK field of RXU_MAP_Ln 178
interconnect architecture for RapidIO 18
LETTER field of RXU_MAP_Ln 178
interfacing two 1x or 4x devices 18
letter number associated with logical/transport error 217
INTERRUPT_REQ field of LSUn_REG4 159
letter number masking 45
interrupt approach to messaging protocol 86
letters and mailboxes 43
246 Index SPRUE13A – September 2006
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