Texas Instruments TMS320TCI648x Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for TMS320TCI648x Texas Instruments
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 256 |
| Size: | 2.50 MB |
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Document Outline
- Table of Contents
- Preface
- 1 Overview
- 2 SRIO Functional Description
- 2.1 Overview
- 2.2 SRIO Pins
- 2.3 Functional Operation
- 2.3.1 Component Block Diagram
- 2.3.2 SERDES Macro and its Configurations
- 2.3.3 Direct I/O Operation
- 2.3.4 Message Passing
- 2.3.5 Maintenance
- 2.3.6 Doorbell Operation
- 2.3.7 Atomic Operations
- 2.3.8 Congestion Control
- 2.3.9 Endianness
- 2.3.10 Reset and Power Down
- 2.3.11 Emulation
- 2.3.12 TX Buffers, Credit, and Packet Reordering
- 2.3.13 Initialization Example
- 2.3.14 Bootload Capability
- 2.3.15 RX Multicast Support, Daisy Chain Operation and Packet Forwarding
- 3 Logical/Transport Error Handling and Logging
- 4 Interrupt Conditions
- 5 SRIO Registers
- 5.1 Introduction
- 5.2 Peripheral Identification Register (PID)
- 5.3 Peripheral Control Register (PCR)
- 5.4 Peripheral Settings Control Register (PER_SET_CNTL)
- 5.5 Peripheral Global Enable Register (GBL_EN)
- 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT)
- 5.7 Block n Enable Register (BLKn_EN)
- 5.8 Block n Enable Status Register (BLKn_EN_STAT)
- 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1)
- 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2)
- 5.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn)
- 5.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn)
- 5.13 SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)
- 5.14 SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL)
- 5.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)
- 5.16 DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR)
- 5.17 DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR)
- 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR)
- 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)
- 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)
- 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)
- 5.22 LSU Interrupt Condition Status Register (LSU_ICSR)
- 5.23 LSU Interrupt Condition Clear Register (LSU_ICCR)
- 5.24 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR)
- 5.25 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR)
- 5.26 DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and DOORBELLn_ICRR2)
- 5.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2)
- 5.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2)
- 5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3)
- 5.30 Error, Reset, and Special Event Interrupt Condition Routing Registers (ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3)
- 5.31 Interrupt Status Decode Register (INTDSTn_DECODE)
- 5.32 INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL)
- 5.33 LSUn Control Register 0 (LSUn_REG0)
- 5.34 LSUn Control Register 1 (LSUn_REG1)
- 5.35 LSUn Control Register 2 (LSUn_REG2)
- 5.36 LSUn Control Register 3 (LSUn_REG3)
- 5.37 LSUn Control Register 4 (LSUn_REG4)
- 5.38 LSUn Control Register 5 (LSUn_REG5)
- 5.39 LSUn Control Register 6 (LSUn_REG6)
- 5.40 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS)
- 5.41 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP)
- 5.42 Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP)
- 5.43 Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP)
- 5.44 Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP)
- 5.45 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)
- 5.46 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0–7])
- 5.47 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN)
- 5.48 Receive CPPI Control Register (RX_CPPI_CNTL)
- 5.49 Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0–3])
- 5.50 Mailbox to Queue Mapping Registers (RXU_MAP_Ln and RXU_MAP_Hn)
- 5.51 Flow Control Table Entry Register n (FLOW_CNTLn)
- 5.52 Device Identity CAR (DEV_ID)
- 5.53 Device Information CAR (DEV_INFO)
- 5.54 Assembly Identity CAR (ASBLY_ID)
- 5.55 Assembly Information CAR (ASBLY_INFO)
- 5.56 Processing Element Features CAR (PE_FEAT)
- 5.57 Source Operations CAR (SRC_OP)
- 5.58 Destination Operations CAR (DEST_OP)
- 5.59 Processing Element Logical Layer Control CSR (PE_LL_CTL)
- 5.60 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR)
- 5.61 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR)
- 5.62 Base Device ID CSR (BASE_ID)
- 5.63 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK)
- 5.64 Component Tag CSR (COMP_TAG)
- 5.65 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD)
- 5.66 Port Link Time-Out Control CSR (SP_LT_CTL)
- 5.67 Port Response Time-Out Control CSR (SP_RT_CTL)
- 5.68 Port General Control CSR (SP_GEN_CTL)
- 5.69 Port Link Maintenance Request CSR n (SPn_LM_REQ)
- 5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP)
- 5.71 Port Local AckID Status CSR n (SPn_ACKID_STAT)
- 5.72 Port Error and Status CSR n (SPn_ERR_STAT)
- 5.73 Port Control CSR n (SPn_CTL)
- 5.74 Error Reporting Block Header Register (ERR_RPT_BH)
- 5.75 Logical/Transport Layer Error Detect CSR (ERR_DET)
- 5.76 Logical/Transport Layer Error Enable CSR (ERR_EN)
- 5.77 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT)
- 5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT)
- 5.79 Logical/Transport Layer Device ID Capture CSR (ID_CAPT)
- 5.80 Logical/Transport Layer Control Capture CSR (CTRL_CAPT)
- 5.81 Port-Write Target Device ID CSR (PW_TGT_ID)
- 5.82 Port Error Detect CSR n (SPn_ERR_DET)
- 5.83 Port Error Rate Enable CSR n (SPn_RATE_EN)
- 5.84 Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0)
- 5.85 Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1)
- 5.86 Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2)
- 5.87 Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3)
- 5.88 Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4)
- 5.89 Port Error Rate CSR n (SPn_ERR_RATE)
- 5.90 Port Error Rate Threshold CSR n (SPn_ERR_THRESH)
- 5.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER)
- 5.92 Port IP Mode CSR (SP_IP_MODE)
- 5.93 Port IP Prescaler Register (IP_PRESCAL)
- 5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3])
- 5.95 Port Reset Option CSR n (SPn_RST_OPT)
- 5.96 Port Control Independent Register n (SPn_CTL_INDEP)
- 5.97 Port Silence Timer n Register (SPn_SILENCE_TIMER)
- 5.98 Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS)
- 5.99 Port Control Symbol Transmit n Register (SPn_CS_TX)
- Index