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14 bootload capability, 1 configuration and operation – Texas Instruments TMS320TCI648x User Manual

Page 79

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2.3.14

Bootload Capability

2.3.14.1

Configuration and Operation

SRIO Functional Description

SRIO_REGS->SP_RT_CTL

= 0xFFFFFF00;

// long

SRIO_REGS->SP_GEN_CTL

= 0x40000000;

// agent, master, undiscovered

SRIO_REGS->SP0_CTL

= 0x00600000;

// enable i/o

SRIO_REGS->SP1_CTL

= 0x00600000;

// enable i/o

SRIO_REGS->SP2_CTL

= 0x00600000;

// enable i/o

SRIO_REGS->SP3_CTL

= 0x00600000;

// enable i/o

SRIO_REGS->ERR_DET

= 0x00000000 ; // clear

SRIO_REGS->ERR_EN

= 0x00000000 ; // disable

SRIO_REGS->H_ADDR_CAPT

= 0x00000000 ; // clear

SRIO_REGS->ADDR_CAPT

= 0x00000000 ; // clear

SRIO_REGS->ID_CAPT

= 0x00000000 ; // clear

SRIO_REGS->CTRL_CAPT

= 0x00000000 ; // clear

SRIO_REGS->SP_IP_PW_IN_CAPT0 = 0x00000000 ; // clear

SRIO_REGS->SP_IP_PW_IN_CAPT1 = 0x00000000 ; // clear

SRIO_REGS->SP_IP_PW_IN_CAPT2 = 0x00000000 ; // clear

SRIO_REGS->SP_IP_PW_IN_CAPT3 = 0x00000000 ; // clear

//INIT_WAIT wait for lane initialization

Read register to check portx(1-4) OK bit

// polling SRIO_MAC's port_ok bit

rdata = SRIO_REGS->P0_ERR_STAT ;

while ((rdata & 0x00000002) != 0x00000002)

{

rdata = SRIO_REGS->P0_ERR_STAT ;

}

if (srio4p1x_mode){

rdata = SRIO_REGS->P1_ERR_STAT;

while ((rdata & 0x00000002) != 0x00000002)

{

rdata = SRIO_REGS->P1_ERR_STAT;

}

rdata = SRIO_REGS->P2_ERR_STAT;

while ((rdata & 0x00000002) != 0x00000002)

{

rdata = SRIO_REGS->P2_ERR_STAT;

}

rdata = SRIO_REGS->P3_ERR_STAT;

while ((rdata & 0x00000002) != 0x00000002)

{

rdata = SRIO_REGS->P3_ERR_STAT;

}

}

Assert the PEREN bit to enable logical layer data flow

SRIO_REGS->PCR = 0x00000004;

// peren

Figure 41

illustrates the system components involved in bootload operation. It is assumed that an external

device will initiate the bootload data transfer and master the DMA interface. Upon reset, the following
sequence of events must occur:

1. DSP is placed in SRIO boot mode by HW mode pins.
2. Host takes DSP out of reset (POR or RST). The peripheral’s state machines and registers are reset.
3. Internal boot-strap ROM configures device registers, including SERDES, and DMA. DSP executes

internal ROM code to initialize SRIO.

Choice of 4 pin selectable configurations

Optionally, I2C boot can be used to configure SRIO

SPRUE13A – September 2006

Serial RapidIO (SRIO)

79

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