Texas Instruments TMS320TCI648x - Manual (Page 160)

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5.38 LSUn Control Register 5 (LSUn_REG5)
SRIO Registers
There are four of these registers, one for each LSU (see Table 97 ). LSUn_REG5 is shown in Figure 99
and described in Table 98 . For additional programming see Section 2.3.3 .
Table 97. LSUn_REG5 Registers and the Associated LSUs
Register Address Offset Associated LSU
LSU1_REG5 0414h LSU1
LSU2_REG5 0434h LSU2
LSU3_REG5 0454h LSU3
LSU4_REG5 0474h LSU4
Figure 99. LSUn Control Register 5 (LSUn_REG5)
31 16
DRBLL_INFO
R/W-0000h
15 8 7 0
HOP_COUNT PACKET_TYPE
R/W-00h R/W-00h
LEGEND: R/W = Read/Write; -n = Value after reset
Table 98. LSUn Control Register 5 (LSUn_REG5) Field Descriptions
Bit Field Value Description
31–16 DRBLL_INFO 0000h–FFFFh RapidIO doorbell info field for type 10 packets. (see Table 23 )
15–8 HOP_COUNT 00h–FFh RapidIO hop count field specified for type 8 (maintenance) packets
7–0 PACKET_TYPE 00h–FFh The 4 MSBs specify the ftype field for all packet types, and the 4 LSBs
specify the trans field for packet types 2, 5, and 8. See
Section 2.1.2.4
Serial RapidIO (SRIO) 160 SPRUE13A – September 2006
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