Texas Instruments TMS320TCI648x - Manual (Page 234)

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5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3])
SRIO Registers
Four registers are used to capture the incoming 128-bit payload of a Port-Write. These four registers are
shown in
Figure 157 . As can be seen in Table 179 , each of the registers captures one of the four 32-bit
words of the payload.
Figure 157. Port-Write-In Capture CSRs
Port-Write-In Capture CSR 0 (SP_IP_PW_IN_CAPT0) - Address Offset 12010h
31 0
PW_CAPT0
R-00000000h
Port-Write-In Capture CSR 1 (SP_IP_PW_IN_CAPT1) - Address Offset 12014h
31 0
PW_CAPT1
R-00000000h
Port-Write-In Capture CSR 0 (SP_IP_PW_IN_CAPT0) - Address Offset 12018h
31 0
PW_CAPT2
R-00000000h
Port-Write-In Capture CSR 0 (SP_IP_PW_IN_CAPT0) - Address Offset 1201Ch
31 0
PW_CAPT3
R-00000000h
LEGEND: R = Read only; -n = Value after reset
Table 179. Port-Write-In Capture CSR Field Descriptions
Field Value Description
PW_CAPT0 00000000h Word 0 (bits 0 to 31) of the Port-Write payload.
to
FFFFFFFFh
PW_CAPT1 00000000h Word 1 (bits 32 to 63) of the Port-Write payload.
to
FFFFFFFFh
PW_CAPT2 00000000h Word 2 (bits 64 to 95) of the Port-Write payload.
to
FFFFFFFFh
PW_CAPT3 00000000h Word 3 (bits 96 to 127) of the Port-Write payload.
to
FFFFFFFFh
Serial RapidIO (SRIO) 234 SPRUE13A – September 2006
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