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Table 81 – Texas Instruments TMS320TCI648x User Manual

Page 148

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SRIO Registers

Table 81. LSU Interrupt Condition Routing Register Field Descriptions

Field

Value

Description

ICRx

Interrupt condition routing. Routes the associated LSU interrupt request to one of eight interrupt

(x = 0 to 31)

destinations (INTDST0–INTDST7). Bits ICR0–ICR7 are for LSU1; bits ICR8–ICR15, for LSU2; bits
ICR16–ICR23, for LSU3; bits ICR24–ICR31, for LSU4.

0000b

INTDST0

0001b

INTDST1

0010b

INTDST2

0011b

INTDST3

0100b

INTDST4

0101b

INTDST5

0110b

INTDST6

0111b

INTDST7

1xxxb

Reserved

Serial RapidIO (SRIO)

148

SPRUE13A – September 2006

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