Txdma_cp), Descriptions, Section 5.42 – Texas Instruments TMS320TCI648x User Manual
Page 165
www.ti.com
5.42 Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP)
SRIO Registers
There are sixteen of these registers (see
). QUEUEn_TXDMA_CP is shown in
and
described in
. For additional programming information, see
.
Table 106. QUEUEn_TXDMA_CP Registers
Register
Address Offset
QUEUE0_TXDMA_CP
0580h
QUEUE1_TXDMA_CP
0584h
QUEUE2_TXDMA_CP
0588h
QUEUE3_TXDMA_CP
058Ch
QUEUE4_TXDMA_CP
0590h
QUEUE5_TXDMA_CP
0594h
QUEUE6_TXDMA_CP
0598h
QUEUE7_TXDMA_CP
059Ch
QUEUE8_TXDMA_CP
05A0h
QUEUE9_TXDMA_CP
05A4h
QUEUE10_TXDMA_CP
05A8h
QUEUE11_TXDMA_CP
05ACh
QUEUE12_TXDMA_CP
05B0h
QUEUE13_TXDMA_CP
05B4h
QUEUE14_TXDMA_CP
05B8h
QUEUE15_TXDMA_CP
05BCh
Figure 104. Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP)
31
0
TX_CP
R/W-00000000h
LEGEND: R/W = Read/Write; -n = Value after reset
Table 107. Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) Field
Descriptions
Bit
Field
Value
Description
31–0
TX_CP
00000000h
This field is the memory address for the transmit queue completion pointer. This
to
register is written by the DSP core with the buffer descriptor address for the last
FFFFFFFFh
buffer processed by the host during interrupt processing. The port uses the value
written to determine if the interrupt should be deasserted.
SPRUE13A – September 2006
Serial RapidIO (SRIO)
165