Texas Instruments TMS320TCI648x - Manual (Page 6)

List of Figures
1 RapidIO Architectural Hierarchy .......................................................................................... 17
2 RapidIO Interconnect Architecture ....................................................................................... 18
3 Serial RapidIO Device to Device Interface Diagrams
.................................................................
19
4 SRIO Peripheral Block Diagram .......................................................................................... 22
5 Operation Sequence ....................................................................................................... 23
6 1x/4x RapidIO Packet Data Stream (Streaming-Write Class)
........................................................
24
7 Serial RapidIO Control Symbol Format .................................................................................. 24
8 SRIO Component Block Diagram ........................................................................................ 27
9 SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL)
...............................................
28
10 SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) ............................... 31
11 SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) .............................. 33
12 Load/Store Registers for RapidIO (Address Offset: LSU1 400h–418h, LSU2 420h–438h, LSU3
440h–458h, LSU4 460h-478h)
........................................................................................... 36
13 LSU Registers Timing
.....................................................................................................
38
14 Example Burst NWRITE_R ............................................................................................... 39
15 Load/Store Module Data Flow Diagram ................................................................................. 40
16 CPPI RX Scheme for RapidIO
............................................................................................
44
17 Message Request Packet ................................................................................................. 45
18 Mailbox to Queue Mapping Register Pair ............................................................................... 46
19 RX Buffer Descriptor Fields
...............................................................................................
47
20 RX CPPI Mode Explanation .............................................................................................. 49
21 CPPI Boundary Diagram .................................................................................................. 51
22 TX Buffer Descriptor Fields
...............................................................................................
52
23 Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) ................................... 56
24 RX Buffer Descriptors ...................................................................................................... 62
25 TX Buffer Descriptors
......................................................................................................
63
26 Doorbell Operation ......................................................................................................... 64
27 Flow Control Table Entry Registers (Address Offset 0900h–093Ch) ............................................... 66
28 Transmit Source Flow Control Masks
...................................................................................
67
29 Fields Within Each Flow Mask
............................................................................................
67
30 Configuration Bus Example ............................................................................................... 69
31 DMA Example
..............................................................................................................
69
32 GBL_EN (Address 0030h)
................................................................................................
71
33 GBL_EN_STAT (Address 0034h) ........................................................................................ 71
34 BLK0_EN (Address 0038h) ............................................................................................... 72
35 BLK0_EN_STAT (Address 003Ch)
......................................................................................
73
36 BLK1_EN (Address 0040h) ............................................................................................... 73
37 BLK1_EN_STAT (Address 0044h) ....................................................................................... 73
38 BLK8_EN (Address 0078h)
...............................................................................................
73
39 BLK8_EN_STAT (Address 007Ch) ...................................................................................... 73
40 Peripheral Control Register (PCR) - Address Offset 0004h .......................................................... 74
41 Bootload Operation
........................................................................................................
80
42 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) Offsets 0x0090, 0x0098, 0x00A0,
0x00A8
.......................................................................................................................
81
43 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) Offsets 0x0094, 0x009C, 0x00A4,
0x00AC
......................................................................................................................
82
44 Logical/Transport Layer Error Detect CSR (ERR_DET) .............................................................. 83
45 RapidIO DOORBELL Packet for Interrupt Use ......................................................................... 85
46 Doorbell 0 Interrupt Condition Status and Clear Registers
...........................................................
87
47 Doorbell 1 Interrupt Condition Status and Clear Registers ........................................................... 87
48 Doorbell 2 Interrupt Condition Status and Clear Registers ........................................................... 88
49 Doorbell 3 Interrupt Condition Status and Clear Registers
...........................................................
88
6 List of Figures SPRUE13A – September 2006
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