Texas Instruments TMS320TCI648x - Manual (Page 7)

50 RX CPPI Interrupt Condition Status and Clear Registers
.............................................................
89
51 TX CPPI Interrupt Condition Status and Clear Registers ............................................................. 89
52 LSU Interrupt Condition Status and Clear Registers .................................................................. 90
53 Error, Reset, and Special Event Interrupt Condition Status and Clear Registers
.................................
91
54 Doorbell 0 Interrupt Condition Routing Registers ...................................................................... 94
55 RX CPPI Interrupt Condition Routing Registers ........................................................................ 94
56 TX CPPI Interrupt Condition Routing Registers
........................................................................
95
57 LSU Interrupt Condition Routing Registers ............................................................................. 96
58 Error, Reset, and Special Event Interrupt Condition Routing Registers ............................................ 97
59 Interrupt Status Decode Register (INTDSTn_DECODE)
.............................................................
98
60 Interrupt Sources Assigned to ISDR Bits ............................................................................... 98
61 Example Diagram of Interrupt Status Decode Register Mapping .................................................... 99
62 INTDSTn_RATE_CNTL Interrupt Rate Control Register
............................................................
100
63 Peripheral ID Register (PID) - Address Offset 0000h ................................................................ 111
64 Peripheral Control Register (PCR) - Address Offset 0004h ......................................................... 112
65 Peripheral Settings Control Register (PER_SET_CNTL) (Address Offset 0020h)
...............................
113
66 Peripheral Global Enable Register (GBL_EN) (Address Offset 0030h) ........................................... 116
67 Peripheral Global Enable Status Register (GBL_EN_STAT) - Address 0034h .................................. 117
68 Block n Enable Register (BLKn_EN)
...................................................................................
119
69 Block n Enable Status Register (BLKn_EN) .......................................................................... 120
70 RapidIO DEVICEID1 Register (DEVICEID_REG1) (Offset 0080h) ................................................ 121
71 RapidIO DEVICEID2 Register (DEVICEID_REG2) (Offset 0x0084)
...............................................
122
72 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) .......................................... 123
73 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) ............................................. 124
74 SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)
.............................
125
75 SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) ............................. 128
76 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) .............................................. 130
77 Doorbell n Interrupt Condition Status Register (DOORBELLn_ICSR)
.............................................
132
78 Doorbell n Interrupt Condition Clear Register (DOORBELLn_ICCR) .............................................. 133
79 RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) - Address Offset 0240h ...................... 134
80 RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) - Address Offset 0248h
.......................
135
81 TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) - Address Offset 0250h ....................... 136
82 TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) - Address Offset 0258h ........................ 137
83 LSU Interrupt Condition Status Register (LSU_ICSR) - Address Offset 0260h
..................................
138
84 LSU Interrupt Condition Clear Register (LSU_ICCR) - Address Offset 0268h ................................... 141
85 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) - Address
Offset 0270h
...............................................................................................................
142
86 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) - Address
Offset 0278h
...............................................................................................................
143
87 Doorbell n Interrupt Condition Routing Registers ..................................................................... 144
88 RX CPPI Interrupt Condition Routing Registers ...................................................................... 145
89 TX CPPI Interrupt Condition Routing Registers
......................................................................
146
90 LSU Interrupt Condition Routing Registers ............................................................................ 147
91 Error, Reset, and Special Event Interrupt Condition Routing Registers ........................................... 149
92 Interrupt Status Decode Register (INTDSTn_DECODE)
............................................................
150
93 INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL) .............................................. 154
94 LSUn Control Register 0 (LSUn_REG0) ............................................................................... 155
95 LSUn Control Register 1 (LSUn_REG1)
...............................................................................
156
96 LSUn Control Register 2 (LSUn_REG2) ............................................................................... 157
97 LSUn Control Register 3 (LSUn_REG3) ............................................................................... 158
98 LSUn Control Register 4 (LSUn_REG4)
...............................................................................
159
99 LSUn Control Register 5 (LSUn_REG5) ............................................................................... 160
100 LSUn Control Register 6 (LSUn_REG6) ............................................................................... 161
101 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS)
.........................................
162
SPRUE13A – September 2006 List of Figures 7
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