Texas Instruments TMS320TCI648x - Manual (Page 131)

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SRIO Registers
Table 64. SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) Field Descriptions
(continued)
Bit Field Value Description
5–1 MPY PLL multiply. Select PLL multiply factors between 4 and 60.
00000b 4x
00001b 5x
00010b 6x
00011b Reserved
00100b 8x
00101b 10x
00110b 12x
00111b 12.5x
01000b 15x
01001b 20x
01010b 25x
01011b Reserved
01100b Reserved
01111b Reserved
1xxxxb Reserved
0 ENPLL Enable PLL
0 PLL disabled
1 PLL enabled
SPRUE13A – September 2006 Serial RapidIO (SRIO) 131
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