beautypg.com

460h-478h) – Texas Instruments TMS320TCI648x User Manual

Page 36

background image

www.ti.com

LSU _REG0

n

RapidIO Address MSB

Control

31

RapidIO Address LSB/Config_offset

Control

31

0

LSU _REG1

n

DSP Address

Control

31

0

LSU _REG2

n

RSV

Control

31

0

LSU _REG3

n

12 11

Byte_count

OutPortID

Control

31

0

LSU _REG4

n

1

7

Interrupt Req

30

Priority

29

28

xambs

27

26

ID Size

25

24

DestID

23

8

RSV

Drbll Info

Command

31

0

LSU _REG5

n

8 7

Packet Type

16

Hop Count

15

RSV

31

LSU _REG6

n

1

Bsy

5

Completion Code

4

Status

0

0

SRIO Functional Description

Figure 12. Load/Store Registers for RapidIO (Address Offset: LSU1 400h–418h, LSU2 420h–438h, LSU3

440h–458h, LSU4 460h-478h)

The mapping of LSU register fields to RapidIO packet header fields is explained in

Table 14

and

Table 15

.

Table 14

has the fields of the control and command registers (LSUn_REG0 through LSUn_REG5), and

Table 15

has the fields of the status register (LSUn_REG6).

Table 14. LSU Control/Command Register Fields

LSU Register Field

RapidIO Packet Header Field

RapidIO Address MSB

32-bit Extended Address Fields – Packet Types 2, 5, and 6

RapidIO Address

1.

32-bit Address– Packet Types 2, 5, and 6 (Will be used in conjunction with BYTE_COUNT to

LSB/Config_offset

create 64-bit aligned RapidIO packet header address)

2.

24-bit Config_offset Field – Maintenance Packets Type 8 (Will be used in conjunction with
BYTE_COUNT to create 64-bit aligned RapidIO packet header Config_offset). The 2 LSBs of
this field must be zero since the smallest configuration access is 4 bytes.

DSP Address

32-bit DSP byte address. Not available in RapidIO Header.

Byte_Count

Number of data bytes to Read/Write - up to 4K bytes. (Used in conjunction with RapidIO address
to create WRSIZE/RDSIZE and WDPTR in RapidIO packet header.)

000000000000b – 4K bytes

000000000001b – 1 byte

000000000010b – 2 bytes

. . .

111111111111b – 4095 bytes

(Maintenance requests are limited to 4 bytes)

ID Size

RapidIO tt field specifying 8- or 16-bit DeviceIDs.

00b – 8-bit deviceIDs

01b – 16-bit deviceIDs

10b - reserved

11b - reserved

Priority

RapidIO prio field specifying packet priority (0 = lowest, 3 = highest). Request packets should not
be sent at a priority level of 3 to avoid system deadlock. It is the responsibility of the software to
assign the appropriate outgoing priority.

Xamsbs

RapidIO xamsb field specifying the extended address MSBs.

36

Serial RapidIO (SRIO)

SPRUE13A – September 2006

Submit Documentation Feedback