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Section 5.43 – Texas Instruments TMS320TCI648x User Manual

Page 166

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5.43 Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP)

SRIO Registers

There are sixteen of these registers (see

Table 108

). QUEUEn_RXDMA_HDP is shown in

Figure 105

and

described in

Table 109

. For additional programming information, see

Section 2.3.4.1

.

Table 108. QUEUEn_RXDMA_HDP Registers

Register

Address Offset

QUEUE0_RXDMA_HDP

0600h

QUEUE1_RXDMA_HDP

0604h

QUEUE2_RXDMA_HDP

0608h

QUEUE3_RXDMA_HDP

060Ch

QUEUE4_RXDMA_HDP

0610h

QUEUE5_RXDMA_HDP

0614h

QUEUE6_RXDMA_HDP

0618h

QUEUE7_RXDMA_HDP

061Ch

QUEUE8_RXDMA_HDP

0620h

QUEUE9_RXDMA_HDP

0624h

QUEUE10_RXDMA_HDP

0628h

QUEUE11_RXDMA_HDP

062Ch

QUEUE12_RXDMA_HDP

0630h

QUEUE13_RXDMA_HDP

0634h

QUEUE14_RXDMA_HDP

0638h

QUEUE15_RXDMA_HDP

063Ch

Figure 105. Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP)

31

0

RX_HDP

R/W-00000000h

LEGEND: R/W = Read/Write; -n = Value after reset

Table 109. Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP) Field

Descriptions

Bit

Field

Value

Description

31–0

RX_HDP

00000000h

RX Queue Head Descriptor Pointer: This field is the memory address for the first

to

buffer descriptor in the channel receive queue. This field is written by the DSP

FFFFFFFCh

core to initiate queue receive operations and is zeroed by the port when all free
buffers have been used. An error condition results if the DSP core writes this
field when the current field value is nonzero. The address must be 32-bit word
aligned (the 2 LSBs must be 0s).

Serial RapidIO (SRIO)

166

SPRUE13A – September 2006

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