Texas Instruments TMS320C67X/C67X+ DSP User Manual
Texas Instruments Car speakers
Table of contents
Document Outline
- Title Page - SPRU733
- IMPORTANT NOTICE
- Read This First
- Contents
- Figures
- Tables
- Examples
- Chapter 1: Introduction
- Chapter 2: CPU Data Paths and Control
- 2.1 Introduction
- 2.2 General-Purpose Register Files
- 2.3 Functional Units
- 2.4 Register File Cross Paths
- 2.5 Memory, Load, and Store Paths
- 2.6 Data Address Paths
- 2.7 Control Register File
- 2.7.1 Register Addresses for Accessing the Control Registers
- 2.7.2 Pipeline/Timing of Control Register Accesses
- 2.7.3 Addressing Mode Register (AMR)
- 2.7.4 Control Status Register (CSR)
- 2.7.5 Interrupt Clear Register (ICR)
- 2.7.6 Interrupt Enable Register (IER)
- 2.7.7 Interrupt Flag Register (IFR)
- 2.7.8 Interrupt Return Pointer Register (IRP)
- 2.7.9 Interrupt Set Register (ISR)
- 2.7.10 Interrupt Service Table Pointer Register (ISTP)
- 2.7.11 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)
- 2.7.12 E1 Phase Program Counter (PCE1)
- 2.8 Control Register File Extensions
- Chapter 3: Instruction Set
- 3.1 Instruction Operation and Execution Notations
- 3.2 Instruction Syntax and Opcode Notations
- 3.3 Overview of IEEE Standard Single- and Double-Precision Formats
- 3.4 Delay Slots
- 3.5 Parallel Operations
- 3.6 Conditional Operations
- 3.7 Resource Constraints
- 3.7.1 Constraints on Instructions Using the Same Functional Unit
- 3.7.2 Constraints on the Same Functional Unit Writing in the Same Instruction Cycle
- 3.7.3 Constraints on Cross Paths (1X and 2X)
- 3.7.4 Constraints on Loads and Stores
- 3.7.5 Constraints on Long (40-Bit) Data
- 3.7.6 Constraints on Register Reads
- 3.7.7 Constraints on Register Writes
- 3.7.8 Constraints on Floating-Point Instructions
- 3.8 Addressing Modes
- 3.9 Instruction Compatibility
- 3.10 Instruction Descriptions
- Example
- ABS
- ABSDP
- ABSSP
- ADD
- ADDAB
- ADDAD
- ADDAH
- ADDAW
- ADDDP
- ADDK
- ADDSP
- ADDU
- ADD2
- AND
- B displacement
- B register
- B IRP
- B NRP
- CLR
- CMPEQ
- CMPEQDP
- CMPEQSP
- CMPGT
- CMPGT
- CMPGTDP
- CMPGTSP
- CMPGTU
- CMPLT
- CMPLTDP
- CMPLTSP
- CMPLTU
- DPINT
- DPSP
- DPTRUNC
- EXT
- EXTU
- IDLE
- INTDP
- INTDPU
- INTSP
- INTSPU
- LDB(U)
- LDB(U)
- LDDW
- LDH(U)
- LDH(U)
- LDW
- LDW
- LMBD
- MPY
- MPYDP
- MPYH
- MPYHL
- MPYHLU
- MPYHSLU
- MPYHSU
- MPYHU
- MPYHULS
- MPYHUS
- MPYI
- MPYID
- MPYLH
- MPYLHU
- MPYLSHU
- MPYLUHS
- MPYSP
- MPYSPDP
- MPYSP2DP
- MPYSU
- MPYU
- MPYUS
- MV
- MVC
- MVK
- MVKH/MVKLH
- MVKL
- NEG
- NOP
- NORM
- NOT
- OR
- RCPDP
- RCPSP
- RSQRDP
- RSQRSP
- SADD
- SAT
- SET
- SHL
- SHR
- SHRU
- SMPY
- SMPYH
- SMPYHL
- SMPYLH
- SPDP
- SPINT
- SPTRUNC
- SSHL
- SSUB
- STB
- STB
- STH
- STH
- STW
- STW
- SUB
- SUBAB
- SUBAH
- SUBAW
- SUBC
- SUBDP
- SUBSP
- SUBU
- SUB2
- XOR
- ZERO
- Chapter4: Pipeline
- 4.1 Pipeline Operation Overview
- 4.2 Pipeline Execution of Instruction Types
- 4.2.1 Single-Cycle Instructions
- 4.2.2 16 x 16-Bit Multiply Instructions
- 4.2.3 Store Instructions
- 4.2.4 Load Instructions
- 4.2.5 Branch Instructions
- 4.2.6 Two-Cycle DP Instructions
- 4.2.7 Four-Cycle Instructions
- 4.2.8 INTDP Instruction
- 4.2.9 DP Compare Instructions
- 4.2.10 ADDDP/SUBDP Instructions
- 4.2.11 MPYI Instruction
- 4.2.12 MPYID Instruction
- 4.2.13 MPYDP Instruction
- 4.2.14 MPYSPDP Instruction
- 4.2.15 MPYSP2DP Instruction
- 4.3 Functional Unit Constraints
- 4.4 Performance Considerations
- Chapter 5: Interrupts
- 5.1 Overview
- 5.2 Globally Enabling and Disabling Interrupts
- 5.3 Individual Interrupt Control
- 5.4 Interrupt Detection and Processing
- 5.5 Performance Considerations
- 5.6 Programming Considerations
- Appendix A: Instruction Compatibility
- Appendix B: Mapping Between Instruction and Functional Unit
- Appendix C: .D Unit Instructions and Opcode Maps
- Appendix D: .L Unit Instructions and Opcode Maps
- Appendix E: .M Unit Instructions and Opcode Maps
- Appendix F: .S Unit Instructions and Opcode Maps
- Appendix G: No Unit Specified Instructions and Opcode Maps
- Index