Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 358)

Pipeline Execution of Instruction Types
Pipeline 4-26 SPRU733
4.2.8 INTDP Instruction
The INTDP instruction uses the E1 through E5 phases of the pipeline to
complete its operations (see Table 4−10). src2 is read on E1, the lower 32 bits
of the result are written on E4, and the upper 32 bits of the result are written
on E5. The INTDP instruction is executed on the .L unit. The status is written
to the FADCR on E4. Figure 4−20 shows the fetch, decode, and execute
phases of the pipeline that the INTDP instruction uses.
Table 4−10. INTDP Instruction Execution
Pipeline Stage E1 E2 E3 E4 E5
Read src2
Written dst_l dst_h
Unit in use .L
Figure 4−20. INTDP Instruction Phases
PG PS PW PR DP DC E1 E2 E3 E4 E5
4 delay slots