Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 367)

Functional Unit Constraints
4-35 Pipeline SPRU733
Table 4−19 shows the instruction constraints for DP compare instructions
executing on the .S unit.
Table 4−19. DP Compare .S-Unit Instruction Constraints
Instruction Execution
Cycle 1 2 3
DP compare R RW
Instruction Type Subsequent Same-Unit Instruction Executable
Single-cycle Xrw n
DP compare Xr n
2-cycle DP Xrw n
ADDDP/SUBDP Xr n
ADDSP/SUBSP Xr n
Branch † Xr n
Instruction Type Same Side, Different Unit, Both Using Cross Path Executable
Single-cycle Xr n
Load Xr n
Store Xr n
INTDP Xr n
ADDDP/SUBDP Xr n
16 × 16 multiply Xr n
4-cycle Xr n
MPYI Xr n
MPYID Xr n
MPYDP Xr n
Legend: = E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction; n = Next instruction can enter E1 during cycle; Xr = Next instruction cannot enter E1 during cycle-read/
decode constraint; Xrw = Next instruction cannot enter E1 during cycle-read/decode/write constraint
† The branch on register instruction is the only branch instruction that reads a general-purpose register