Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 465)

Index
Index-11 SPRU733
SUBC instruction 3-258
SUBDP instruction 3-260
.L-unit instruction constraints 4-51
.S-unit instruction constraints 4-38
pipeline operation 4-28
SUBSP instruction 3-263
.S-unit instruction constraints 4-37
subtract
conditionally and shift (SUBC) 3-258
floating-point
double-precision (SUBDP) 3-260
single-precision (SUBSP) 3-263
two 16-bit integers on upper and lower register
halves (SUB2) 3-268
using byte addressing mode (SUBAB) 3-253
using halfword addressing mode
(SUBAH) 3-255
using word addressing mode (SUBAW) 3-256
with saturation, two signed integers
(SSUB) 3-234
without saturation
two signed integers (SUB) 3-249
two unsigned integers (SUBU) 3-266
subtract instructions
using circular addressing 3-32
using linear addressing 3-30
SUBU instruction 3-266
syntax, fields and meanings 3-7
T
TMS320 DSP family
applications 1-3
overview 1-2
TMS320C6000 DSP family, overview 1-2
TMS320C67x DSP
architecture 1-7
block diagram 1-7
features 1-4
options 1-4
trademarks iv
traps
invoking a trap 5-26
returning from 5-26
two 16-bit integers
add on upper and lower register halves
(ADD2) 3-65
subtract on upper and lower register halves
(SUB2) 3-268
two-cycle DP instructions, pipeline operation 4-24
U
UND bit 2-27
UNDER bit
in FADCR 2-24
in FMCR 2-31
UNORD bit 2-27
V
VelociTI architecture 1-1
VLIW (very long instruction word) architecture 1-1
X
XOR instruction 3-270
Z
zero a register (ZERO) 3-272
ZERO instruction 3-272