Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 379)

Functional Unit Constraints
4-47 Pipeline SPRU733
Table 4−31 shows the instruction constraints for MPYSP2DP instructions
executing on the .M unit.
Table 4−31. MPYSP2DP .M-Unit Instruction Constraints
Instruction Execution
Cycle 1 2 3 4 5
MPYSP2DP R R W W
Instruction Type Subsequent Same-Unit Instruction Executable
16 × 16 multiply n Xw Xw n
MPYDP Xu n n n
MPYI Xu n n n
MPYID Xu n n n
MPYSP Xw n n n
MPYSPDP Xu n n n
MPYSP2DP Xw n n n
Instruction Type Same Side, Different Unit, Both Using Cross Path Executable
Single-cycle Xr n n n
Load Xr n n n
Store Xr n n n
DP compare Xr n n n
2-cycle DP Xr n n n
Branch Xr n n n
4-cycle Xr n n n
INTDP Xr n n n
ADDDP/SUBDP Xr n n n
Legend: = E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction; n = Next instruction can enter E1 during cycle; Xr = Next instruction cannot enter E1 during cycle−read/
decode constraint; Xw = Next instruction cannot enter E1 during cycle−write constraint; Xu = Next instruction cannot
enter E1 during cycle−other resource conflict