Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 361)

Pipeline Execution of Instruction Types
4-29 Pipeline SPRU733
4.2.11 MPYI Instruction
The MPYI instruction uses the E1 through E9 phases of the pipeline to
complete its operations (see Table 4−13). The sources are read on cycles E1
through E4 and the result is written on E9. The MPYI instruction is executed
on the .M unit. The functional unit latency for the MPYI instruction is 4.
Figure 4−23 shows the fetch, decode, and execute phases of the pipeline that
the MPYI instruction uses.
Table 4−13. MPYI Instruction Execution
Pipeline Stage E1 E2 E3 E4 E5 E6 E7 E8 E9
Read src1
src2 src1
src2 src1
src2 src1
src2
Written dst
Unit in use .M .M .M .M
Figure 4−23. MPYI Instruction Phases
PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9
8 delay slots