Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 418)

Programming Considerations
5-23 Interrupts SPRU733
Example 5−11. Code Using Single Assignment
LDW .D1 *A0,A6
ADD .L1 A1,A2,A3
NOP 3
MPY .M1 A6,A4,A5 ; uses A6
5.6.2 Nested Interrupts
Generally, when the CPU enters an interrupt service routine, interrupts are
disabled. However, when the interrupt service routine is for one of the
maskable interrupts (INT4−INT15), an NMI can interrupt processing of the
maskable interrupt. In other words, an NMI can interrupt a maskable interrupt,
but neither an NMI nor a maskable interrupt can interrupt an NMI.
There may be times when you want to allow an interrupt service routine to be
interrupted by another (particularly higher priority) interrupt. Even though the
processor by default does not allow interrupt service routines to be interrupted
unless the source is an NMI, it is possible to nest interrupts under software
control. To allow nested interrupts, the interrupt service routine must perform
the following initial steps in addition to its normal work of saving any registers
(including control registers) that it modifies:
1) The contents of IRP (or NRP) must be saved
2) The contents of the PGIE bit must be saved
3) The GIE bit must be set to 1
Prior to returning from the interrupt service routine, the code must restore the
registers saved above as follows:
1) The GIE bit must be first cleared to 0
2) The PGIE bit saved value must be restored
3) The IRP (or NRP) saved value must be restored
Although steps 2 and 3 above may be performed in any order, it is important
that the GIE bit is cleared first. This means that the GIE and PGIE bits must
be restored with separate writes to CSR. If these bits are not restored
separately, then it is possible that the PGIE bit is overwritten by nested
interrupt processing just as interrupts are being disabled.
Example 5−12 shows a simple assembly interrupt handler that allows nested
interrupts on the C67x CPU. This example saves its context to the system
stack, pointed to by B15. This assumes that the C runtime conventions are
being followed. The example code is not optimized, to aid in readability.