Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 77)

Parallel Operations
3-17 Instruction Set SPRU733
Example 3−1. Fully Serial p-Bit Pattern in a Fetch Packet
This p-bit pattern:
0 0 0 0 0 0 0 0
Instruction
A
Instruction
B
Instruction
C
Instruction
D
Instruction
E
Instruction
F
Instruction
G
Instruction
H
31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0
results in this execution sequence:
Cycle/Execute
Packet Instructions
1 A
2 B
3 C
4 D
5 E
6 F
7 G
8 H
The eight instructions are executed sequentially.
Example 3−2. Fully Parallel p-Bit Pattern in a Fetch Packet
This p-bit pattern:
1 1 1 1 1 1 1 0
Instruction
A
Instruction
B
Instruction
C
Instruction
D
Instruction
E
Instruction
F
Instruction
G
Instruction
H
31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0
results in this execution sequence:
Cycle/Execute
Packet Instructions
1 A B C D E F G H
All eight instructions are executed in parallel.