Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 52)

Control Register File Extensions
CPU Data Paths and Control 2-26 SPRU733
Table 2−14. Floating-Point Adder Configuration Register (FADCR)
Field Descriptions (Continued)
Bit Description Value Field
7 INEX Inexact results status for .L1.
0
1 Result differs from what would have been computed had the exponent range
and precision been unbounded; never set with INVAL.
6 OVER Result overflow status for .L1.
0 Result does not overflow.
1 Result overflows.
5 INFO Signed infinity for .L1.
0 Result is not signed infinity.
1 Result is signed infinity.
4 INVAL
0 A signed NaN (SNaN) is not a source.
1 A signed NaN (SNaN) is a source. NaN is a source in a floating-point to integer
conversion or when infinity is subtracted from infinity.
3 DEN2 Denormalized number select for .L1 src2.
0 src2 is not a denormalized number.
1 src2 is a denormalized number.
2 DEN1 Denormalized number select for .L1 src1.
0 src1 is not a denormalized number.
1 src1 is a denormalized number.
1 NAN2 NaN select for .L1 src2.
0 src2 is not NaN.
1 src2 is NaN.
0 NAN1 NaN select for .L1 src1.
0 src1 is not NaN.
1 src1 is NaN.