Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 347)

Pipeline Execution of Instruction Types
4-15 Pipeline SPRU733
Table 4−2. Execution Stage Length Description for Each Instruction Type (Continued)
Instruction Type
Execution
phases
MPYSPDP MPYSP2DP
E1 Read src1 and lower
src2 and start
computation Read sources and
start computation
E2 Read src1 and upper
src2 and continue
computation Continue computation
E3 Continue computation Continue computation
E4 Continue computation Continue computation
and write lower
results to register
E5 Continue computation Complete computa-
tion and write upper
results to register
E6 Continue computation
and write lower
results to register
E7 Complete computa-
tion and write upper
results to register
E8
E9
E10
Delay slots 6 4
Functional
unit latency 3 2
Notes: 1) This table assumes that the condition for each instruction is evaluated as true. If the condition is evaluated as
false, the instruction does not write any results or have any pipeline operation after E1.
2) NOP is not shown and has no operation in any of the execution phases.