Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 460)

Index
Index-6 SPRU733
INTSPU instruction 3-122
INVAL bit
in FADCR 2-24
in FAUCR 2-27
in FMCR 2-31
IRP 2-19
ISn bit 2-20
ISR 2-20
ISTB bits 2-21
ISTP 2-21
L
latency 3-14
LDB instruction
5-bit unsigned constant offset or register
offset 3-123
15-bit unsigned constant offset 3-126
LDBU instruction
5-bit unsigned constant offset or register
offset 3-123
15-bit constant offset 3-126
LDDW instruction 3-128
constraints 3-29
LDDW instruction with long write instruction,
D-unit instruction constraints 4-55
LDH instruction
5-bit unsigned constant offset or register
offset 3-131
15-bit unsigned constant offset 3-134
LDHU instruction
5-bit unsigned constant offset or register
offset 3-131
15-bit unsigned constant offset 3-134
LDW instruction
5-bit unsigned constant offset or register
offset 3-136
15-bit unsigned constant offset 3-139
leftmost bit detection (LMBD) 3-141
linear addressing mode 3-30
add instructions 3-30
load instructions 3-30
store instructions 3-30
subtract instructions 3-30
LMBD instruction 3-141
load
byte
from memory with a 5-bit unsigned constant
offset or register offset (LDB and
LDBU) 3-123
from memory with a 15-bit unsigned constant
offset (LDB and LDBU) 3-126
doubleword from memory with an unsigned
constant offset or register offset
(LDDW) 3-128
halfword
from memory with a 5-bit unsigned constant
offset or register offset (LDH and
LDHU) 3-131
from memory with a 15-bit unsigned constant
offset (LDH and LDHU) 3-134
word
from memory with a 5-bit unsigned constant
offset or register offset (LDW) 3-136
from memory with a 15-bit unsigned constant
offset (LDW) 3-139
load and store paths, CPU 2-6
load instructions
.D-unit instruction constraints 4-52
block diagram 4-21
conflicts 3-22
pipeline operation 4-20
syntax for indirect addressing 3-32
using circular addressing 3-31
using linear addressing 3-30
load or store to the same memory location,
rules 4-19
load paths 2-6
logical shift right (SHRU) 3-217
M
memory
introduction 1-8
paths 2-6
memory bank hits 4-62
memory considerations 4-60
memory bank hits 4-62
memory stalls 4-61
memory paths 2-6
memory stalls 4-61