Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 335)

Pipeline Operation Overview
4-3 Pipeline SPRU733
Figure 4−2. Fetch Phases of the Pipeline
PR PW PS PG
PW
Memory
PS
PR
PG
Registers
units
Functional
(a) (b)
CPU
PR
PW
PS
PG
256
MVK LDW LDW SHL ADD MVK LDW LDW
NOP
MVK
MV
B SADD
SMPYH
SADD
SHR
SMPY
SHR
SMPYH
LDW
LDW
LDW
LDW
MVK B SMPY SMPYH MV MVKLH LDW LDW
Fetch
SMPYH
Decode
(c)
4.1.2 Decode
The decode phases of the pipeline are:
- DP: Instruction dispatch
- DC: Instruction decode
In the DP phase of the pipeline, the fetch packets are split into execute pack-
ets. Execute packets consist of one instruction or from two to eight parallel
instructions. During the DP phase, the instructions in an execute packet are
assigned to the appropriate functional units. In the DC phase, the the source
registers, destination registers, and associated paths are decoded for the
execution of the instructions in the functional units.