Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 53)

Control Register File Extensions
2-27 CPU Data Paths and Control SPRU733
2.8.2 Floating-Point Auxiliary Configuration Register (FAUCR)
The floating-point auxiliary register (FAUCR) contains fields that specify
underflow or overflow, the rounding mode, NaNs, denormalized numbers, and
inexact results for instructions that use the .S functional units. FAUCR has a
set of fields specific to each of the .S units: .S2 uses bits 31−16 and .S1 uses
bits 15−0. FAUCR is shown in Figure 2−15 and described in Table 2−15.
Note:
For the C67x+ DSP, the ADDSP, ADDDP, SUBSP, and SUBDP instructions
executing in the .S functional unit use the rounding mode from and set the
warning bits in the floating-point adder configuration register (FADCR). The
warning bits in FADCR are the logical-OR of the warnings produced on the
.L functional unit and the warnings produced by the ADDSP/ADDDP/
SUBSP/SUBDP instructions on the .S functional unit (but not other instruc-
tions executing on the .S functional unit).
Figure 2−15. Floating-Point Auxiliary Configuration Register (FAUCR)
31 27 26 25 24 23 22 21 20 19 18 17 16
Reserved DIV0 UNORD UND INEX OVER INFO INVAL DEN2 DEN1 NAN2 NAN1
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 11 10 9 8 7 6 5 4 3 2 1 0
Reserved DIV0 UNORD UND INEX OVER INFO INVAL DEN2 DEN1 NAN2 NAN1
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R = Readable by the MVC instruction; W = Writeable by the MVC instruction; -n = value after reset
Table 2−15. Floating-Point Auxiliary Configuration Register (FAUCR)
Field Descriptions
Bit Field Value Description
31−27 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
26 DIV0 Source to reciprocal operation for .S2.
0 0 is not source to reciprocal operation.
1 0 is source to reciprocal operation.