Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 368)

Functional Unit Constraints
Pipeline 4-36 SPRU733
Table 4−20 shows the instruction constraints for 2-cycle DP instructions exe-
cuting on the .S unit.
Table 4−20. 2-Cycle DP .S-Unit Instruction Constraints
Instruction Execution
Cycle 1 2 3
2-cycle RW W
Instruction Type Subsequent Same-Unit Instruction Executable
Single-cycle Xw n
DP compare n n
2-cycle DP Xw n
ADDDP/SUBDP n
ADDSP/SUBSP n
Branch n n
Instruction Type Same Side, Different Unit, Both Using Cross Path Executable
Single cycle n n
Load n n
Store n n
INTDP n n
ADDDP/SUBDP n n
16 × 16 multiply n n
4-cycle n n
MPYI n n
MPYID n n
MPYDP n n
Legend: = E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction; n = Next instruction can enter E1 during cycle; Xw = Next instruction cannot enter E1 during cycle-write
constraint